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ESE 461: Design Automation for Integrated Circuit Systems
Announcements
Course Administrivia
Course:
ESE 461A, Fall 2016, 3 Units
Instructional Staff:
Xuan Zhang (Instructor)
Dengxue Yan (TA)
Homepage:
http://classes.engineering.wustl.edu/ese461/
Lecture:
Green L0160, MoWe: 2:30 PM - 4:00 PM
Office Hours:
Green 2160F, Tu: 4:00 PM - 5:00 PM
Green 2160F, Th: 3:30 PM - 5:00 PM
Course Description
Integrated systems provide the core technology that power today's most
advanced devices and electronics: smart phones, wearable devices,
autonomous robots, and cars, aerospace or medical electronics. These
systems often consist of silicon microchips made up by billions of
transistors and contain various components such as microprocessors,
digital signal processors (DSPs), hardware accelerators, memories, and
I/O interfaces. Therefore design automation is critical to tackle the
design complexity at the system level.
The objectives of this course are to;
1) provide a general understanding of design automation for very large scale integrated (VLSI) systems;
2) introduce the basic algorithms used in VLSI design and optimization;
3) expose students to the design automation techniques used in
the best-known academic and commercial systems, as well as the hot
research topics and problems in the field.
Topics
covered include digital integrated circuit design flow, logic
synthesis, physical design, high-level synthesis, circuit simulation
and optimization, timing analysis, power delivery network analysis.
Assignments include homework, mini-projects, term paper and group
project.
Schedule (Tentative)
| Lecture |
Date |
Week |
Topics |
Note
|
| 1 |
Aug 29 |
1(a) |
Introduction and Logistics (PDF)
|
|
| 2 |
Aug 31 |
1(b) |
Review on Digital Logic (PART 1) (PDF) |
HW #1 Out |
| 3 |
Sep 5 |
2(a) |
Labor day
|
|
| 4 |
Sep 7 |
2(b) |
Review on Digital Logic (PART 2) (PDF)
|
HW #2 Out |
| 5 |
Sep 12 |
3(a) |
Review on Digital Logic (PART 3) (PDF)
|
|
| 6 |
Sep 14 |
3(b) |
Quiz Review; Linux and VCS Tutorial (PDF)
|
HW #3 Out |
| 7 |
Sep 16 |
4(a) |
Verilog HDL (PART 1) (PDF)
|
Lab #1 Out
|
| 8 |
Sep 21 |
4(b) |
Verilog HDL (PART 2) (PDF) |
Lab #2 Out
|
| 9 |
Sep 26 |
5(a) |
Overview of VLSI Design Flow (PDF) |
Lab #3 Out
|
| 10 |
Sep 28 |
5(b) |
Tcl Basics and Logic Synthesis Intro (PDF)
|
|
| 11 |
Oct 3 |
6(a) |
Logic Synthesis (PART 1) (PDF)
|
|
| 12 |
Oct 5 |
6(b) |
Logic Synthesis (PART 2) (PDF)
|
Lab #4 Out |
| 13 |
Oct 10 |
7(a) |
Timing Analysis (PART 1) (PDF)
|
|
| 14 |
Oct 12 |
7(b) |
Timing Analysis (PART 2) (PDF)
|
|
| 15 |
Oct 17 |
8(a) |
Fall break
|
|
| 16 |
Oct 19 |
8(b) |
Class Project Introduction (PDF)
|
Class Project (PDF)
|
| 17 |
Oct 24 |
9(a) |
Physical Design, (Part 1) (PDF) |
| 18 |
Oct 24 |
9(b) |
Physical Design, (Part 2) (PDF) |
| 19 |
Oct 31 |
10(a) |
Parasitic Extraction and Packaging (PDF)
|
| 20 |
Nov 2 |
10(b) |
Design For Test (DFT) (PDF)
|
| 21 |
Nov 7 |
11(a) |
Team meeting
|
| 22 |
Nov 9 |
11(b) |
Performance Optimization (PPT)
|
| 23 |
Nov 14 |
12(a) |
Power Optimization (Part 1) (PDF)
|
| 24 |
Nov 16 |
12(b) |
Power Optimization (Part 2) (PDF) |
| 25 |
Nov 21 |
13(a) |
Group Meeting |
| 26 |
Nov 23 |
13(b) |
Thanksgiving |
| 27 |
Nov 28 |
14(a) |
Design Compiler in Depth (PDF) |
| 28 |
Nov 30 |
14(b) |
Group Meeting |
| 29 |
Dec 5 |
15(a) |
Encounter in Depth and Conclusion (PDF) |
| 30 |
Dec 7 |
15(b) |
Presentation |
Prerequisites
The curricular prequisites for this class include ESE 232
(Introduction to Electronic Circuits), ESE 260 (Introduction
to Digital Logic and Computer Design), and experience with register-transfer
level (RTL) design and hardware description language (e.g. verilog, VHDL),
or permission from the instructors.
Although not required, familiarity with the subjects in the following
courses are a plus: ESE 362 (Computer Architecture).
In general, students are expected to have a firm grasp on digital and
analog circuits, be familiar with embedded system programming, and know
their way around the Linux system. In addition, success in this course
will require substantial reading and hacking, and a high degree of
patience and determination.
Grading
| Engagement |
5% |
| Review Quiz |
10% |
| Homework |
10% |
| Labs |
40% |
| Final Project |
35% |
Policy
| 90% or above |
A |
| 80% - 89% |
B |
| 65% - 79% |
C |
| 45% - 64% |
D |
| 44% or below |
F |
Resources
- Tutorial on Remote Logging to Linux Lab
- Tutorial on Synopsys VCS
- Tutorial on Design Compiler
- Tutorial on Encounter
- Reference on performance optimization(HDL Coding Guidelines)
- Reference on performance optimization(ProASIC PLUS Design Optimization)
- Reference on performance optimization(Writing Successful RTL Descriptions in Verilog)
- Brief tutorial on how to simulate your synthesized Verilog using VCS
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