Difference between revisions of "Lecture Notes"
From CSE460t Wiki
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*[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] | *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] | ||
*[[media:Oscillators.pdf|Oscillators]] | *[[media:Oscillators.pdf|Oscillators]] | ||
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| + | *[[media:Metastability_Lecture.pdf|Metastability Lecture]] | ||
| + | *[[media:Metastability_Lecture.pdf|David M. Zar Metastability Lecture]] | ||
| + | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
| + | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
*[[media:NOR_Latch.jpg|NOR Latch]] | *[[media:NOR_Latch.jpg|NOR Latch]] | ||
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*[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] | *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] | ||
*[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] | *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] | ||
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*[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] | *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] | ||
*[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] | *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] | ||
*[[media:Kohavi.pdf|State Assignment]] | *[[media:Kohavi.pdf|State Assignment]] | ||
*[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] | *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] | ||
Revision as of 18:39, 1 April 2014
LOGIC MINIMIZATION
- Standard Cell Example
- Karnaugh Maps
- Synthesis of Two-Level Circuits
- Quine-McCluskey Example
- UCP Reduction Techniques
http://en.wikipedia.org/wiki/Petrick%27s_method
- Don't Cares
- Multiple Output Functions
- Iterated Consensus
- Boole's Expansion Theorem
- Decomposition By Expansion
http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf
http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer
- Espresso Example (Quine-McCluskey Example)
- Espresso Example Output (Quine-McCluskey Example)
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- Espresso Arctan Bit 0 Example
- Espresso Arctan Bit 0 Example Output
http://www.mosis.com/pages/design/flows/design-flow-scmos-kits
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic Default Settings
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings
- VHDL Example 2 (Quine-McCluskey Example)
- VHDL Example 2 Synthesized RTL Schematic Default Settings
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings
- VHDL Example 3 (12-bit Arctan Function)
- VHDL Example 4 (12-bit Arctan Function MSB)
- VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)
- VHDL Example 5 (12-bit Arctan Function Bit 10)
- VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)
- VHDL Example 6 (12-bit Arctan Function Bit 9)
- VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)
- VHDL Example 7 (12-bit Arctan Function Bit 8)
- VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)
- VHDL Example 8 (12-bit Arctan Function Bit 0)
- VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)
- VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)
- VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)
- VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)
- VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)
- VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)
- VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)
- VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)
- VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)
- VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)
- Bit Zero Optimal LUTS (85 LUTs Is Optimal)
- Francis Paper
- Cong Optimality Paper
- Altera vs. Xilinx
- Xilinx vs. Altera
- Altera Logic Efficiency Analysis
- Altera FPGA Architecture White Paper
SEQUENTIAL SYSTEMS
- State Equal Output Moore Example
- State Equal Output Moore Example VHDL
- State Equal Output Moore Example Simulation
- State Equal Output Moore Example Synthesis Report Default Settings
- State Equal Output Moore Example Technology Map Schematic Default Settings
- ISE Screenshot: Generating Post Place-and-Route Simulation Model
- ISE Screenshot: Simulating Post Place-and-Route Simulation Model
- State Equal Output Moore Example Post Place-and-Route Simulation
- State Equal Output Moore Example Post Place-and-Route Simulation 2
- State Equal Output Moore Example 2 VHDL
- State Equal Output Moore Example 2 Simulation
- State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User
- State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User
- State Equal Output Moore Example 3 VHDL
- State Equal Output Moore Example 3 Simulation
- State Equal Output Moore Example 3 Synthesis Report Default Settings
- State Equal Output Moore Example 3 Technology Map Schematic Default Settings
- State Equal Output Moore Example 4 VHDL
- State Equal Output Moore Example 4 Simulation
- State Equal Output Moore Example 4 Synthesis Report Default Settings
- State Equal Output Moore Example 4 Technology Map Schematic Default Settings
- Figure 7.4 (4 States)
- Figure 7.4 VHDL Description Version 1
- Xilinx Spartan 6 Technology Map Schematic Default Settings
- Default Version 1 Synthesis Report
- Version 1 ModelSim Simulation
- Figure 7.4 VHDL Description Version 2
- Default Version 2 Synthesis Report
- Figure 7.4 VHDL Description Version 3
- Default Version 3 Synthesis Report
- Figure 7.4 (3 States)
- VHDL Description Version 4 (3 States)
- Version 4 ModelSim Simulation
- Default Version 4 Synthesis Report
- XST User Guide (See Page 276 for Compact State Encoding)
- Figure 7.4 (5 States)
- VHDL Description Version 5 (5 States)
- Default Version 5 Synthesis Report
- Definitions and Theorems for Sequential Machines
- Minimizing Completely Specified Machines
- Simplification of Completely Specified Machines by Implication Tables
- Simplification of Incompletely Specified Machines
- Simplification of Incompletely Specified Machines 1
- Simplification of Incompletely Specified Machines 2
- Prime Compatibles Example from Hachtel and Somenzi (Revised)
- BCP Reduction Techniques
- State Assignment
FINITE AUTOMATA
http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf
ASYNCHRONOUS CIRCUITS AND METASTABILITY
- Metastability Lecture
- David M. Zar Metastability Lecture
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
