Release 13.3 - xst O.76xd (nt) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.23 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.23 secs --> Reading design: figure7dot4.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "figure7dot4.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "figure7dot4" Output Format : NGC Target Device : xc6slx75t-2-fgg676 ---- Source Options Top Module Name : figure7dot4 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "C:\VHDL\Example15\figure7dot4.vhd" into library work Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity (architecture ) from library . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "c:/vhdl/example15/figure7dot4.vhd". Found 2-bit register for signal . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Clock | clk (rising_edge) | | Reset | reset_h (positive) | | Reset type | synchronous | | Reset State | s1 | | Power Up State | s1 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with user encoding. ------------------- State | Encoding ------------------- s1 | 00 s3 | 01 s4 | 10 ------------------- Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block figure7dot4, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 2 Flip-Flops : 2 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : figure7dot4.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 3 # LUT3 : 3 # FlipFlops/Latches : 2 # FDR : 2 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 3 # IBUF : 2 # OBUF : 1 Device utilization summary: --------------------------- Selected Device : 6slx75tfgg676-2 Slice Logic Utilization: Number of Slice Registers: 2 out of 93296 0% Number of Slice LUTs: 3 out of 46648 0% Number used as Logic: 3 out of 46648 0% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 5 Number with an unused Flip Flop: 3 out of 5 60% Number with an unused LUT: 2 out of 5 40% Number of fully used LUT-FF pairs: 0 out of 5 0% Number of unique control sets: 1 IO Utilization: Number of IOs: 4 Number of bonded IOBs: 4 out of 348 1% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 2 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 1.723ns (Maximum Frequency: 580.383MHz) Minimum input arrival time before clock: 2.631ns Maximum output required time after clock: 5.242ns Maximum combinational path delay: 6.150ns Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 1.723ns (frequency: 580.383MHz) Total number of paths / destination ports: 4 / 2 ------------------------------------------------------------------------- Delay: 1.723ns (Levels of Logic = 1) Source: state_FSM_FFd1 (FF) Destination: state_FSM_FFd2 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: state_FSM_FFd1 to state_FSM_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 3 0.525 0.874 state_FSM_FFd1 (state_FSM_FFd1) LUT3:I1->O 1 0.250 0.000 state_FSM_FFd2-In1 (state_FSM_FFd2-In) FDR:D 0.074 state_FSM_FFd2 ---------------------------------------- Total 1.723ns (0.849ns logic, 0.874ns route) (49.3% logic, 50.7% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 4 / 4 ------------------------------------------------------------------------- Offset: 2.631ns (Levels of Logic = 2) Source: input (PAD) Destination: state_FSM_FFd2 (FF) Destination Clock: clk rising Data Path: input to state_FSM_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 1.328 0.994 input_IBUF (input_IBUF) LUT3:I0->O 1 0.235 0.000 state_FSM_FFd2-In1 (state_FSM_FFd2-In) FDR:D 0.074 state_FSM_FFd2 ---------------------------------------- Total 2.631ns (1.637ns logic, 0.994ns route) (62.2% logic, 37.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 2 / 1 ------------------------------------------------------------------------- Offset: 5.242ns (Levels of Logic = 2) Source: state_FSM_FFd1 (FF) Destination: output (PAD) Source Clock: clk rising Data Path: state_FSM_FFd1 to output Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 3 0.525 0.874 state_FSM_FFd1 (state_FSM_FFd1) LUT3:I1->O 1 0.250 0.681 output1 (output_OBUF) OBUF:I->O 2.912 output_OBUF (output) ---------------------------------------- Total 5.242ns (3.687ns logic, 1.555ns route) (70.3% logic, 29.7% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Delay: 6.150ns (Levels of Logic = 3) Source: input (PAD) Destination: output (PAD) Data Path: input to output Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 1.328 0.994 input_IBUF (input_IBUF) LUT3:I0->O 1 0.235 0.681 output1 (output_OBUF) OBUF:I->O 2.912 output_OBUF (output) ---------------------------------------- Total 6.150ns (4.475ns logic, 1.675ns route) (72.8% logic, 27.2% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 1.723| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 14.00 secs Total CPU time to Xst completion: 14.24 secs --> Total memory usage is 194044 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)