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| − | + | LOGIC MINIMIZATION | |
| − | + | *[[media:Standard_Cell.JPG|Standard Cell Example]] | |
| − | + | *[[media:K_Maps.pdf|Karnaugh Maps]] | |
| − | + | *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] | |
| − | + | *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] | |
| − | + | *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] | |
| − | |||
| − | |||
| − | |||
| − | [http://www. | + | http://en.wikipedia.org/wiki/Petrick%27s_method |
| − | + | ||
| + | *[[media:Don't_Cares.pdf|Don't Cares]] | ||
| + | *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] | ||
| + | *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] | ||
| + | *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] | ||
| + | *[[media:Decomposition_By_Expansion.pdf|Decomposition By Expansion]] | ||
| + | |||
| + | http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf | ||
| + | |||
| + | http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer | ||
| + | |||
| + | *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] | ||
| + | *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] | ||
| + | *[[media:CyclicExample.txt|Espresso Cyclic Example]] | ||
| + | *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] | ||
| + | *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] | ||
| + | *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] | ||
| + | |||
| + | http://www.mosis.com/pages/design/flows/design-flow-scmos-kits | ||
| + | |||
| + | *[[media:Technology_Mapping.pdf|Technology Mapping for Standard Cells]] | ||
| + | |||
| + | *[[media:Example1.vhd|VHDL Example 1]] | ||
| + | *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] | ||
| + | *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] | ||
| + | *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] | ||
| + | *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] | ||
| + | *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] | ||
| + | *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] | ||
| + | *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] | ||
| + | *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] | ||
| + | *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] | ||
| + | *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] | ||
| + | *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] | ||
| + | *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] | ||
| + | *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] | ||
| + | *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] | ||
| + | *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] | ||
| + | *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] | ||
| + | *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] | ||
| + | *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] | ||
| + | *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] | ||
| + | *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] | ||
| + | *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] | ||
| + | *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] | ||
| + | *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] | ||
| + | *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] | ||
| + | *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] | ||
| + | *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] | ||
| + | *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] | ||
| + | *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] | ||
| + | *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] | ||
| + | *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] | ||
| + | *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] | ||
| + | *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] | ||
| + | |||
| + | *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] | ||
| + | *[[media:Ieeetc86.pdf|Bryant Paper]] | ||
| + | |||
| + | http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true | ||
| + | |||
| + | |||
| + | SEQUENTIAL SYSTEMS | ||
| + | *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] | ||
| + | *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] | ||
| + | *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] | ||
| + | *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] | ||
| + | *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] | ||
| + | *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] | ||
| + | *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] | ||
| + | *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] | ||
| + | *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] | ||
| + | *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] | ||
| + | *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] | ||
| + | *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] | ||
| + | *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] | ||
| + | *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] | ||
| + | *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] | ||
| + | *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] | ||
| + | *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] | ||
| + | *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] | ||
| + | *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] | ||
| + | *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] | ||
| + | *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] | ||
| + | |||
| + | |||
| + | *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] | ||
| + | *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] | ||
| + | *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] | ||
| + | *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] | ||
| + | *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] | ||
| + | *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] | ||
| + | *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] | ||
| + | *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] | ||
| + | *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] | ||
| + | *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] | ||
| + | *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] | ||
| + | *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] | ||
| + | *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] | ||
| + | *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] | ||
| + | *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] | ||
| + | *[[media:Figure7dot4WithFiveStates.vhd|VHDL Description Version 5 (5 States)]] | ||
| + | *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] | ||
| + | |||
| + | |||
| + | *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] | ||
| + | *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] | ||
| + | *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] | ||
| + | *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] | ||
| + | *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] | ||
| + | *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] | ||
| + | *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] | ||
| + | *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] | ||
| + | *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] | ||
| + | *[[media:State_Assignment.pdf|State Assignment]] | ||
| + | |||
| + | |||
| + | ASYNCHRONOUS CIRCUITS AND METASTABILITY | ||
| + | |||
| + | *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] | ||
| + | *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] | ||
| + | *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] | ||
| + | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
| + | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
| + | *[[media:Metastability_Lecture.pdf|Metastability]] | ||
| + | *[[media:CDC_Lecture_2016.pdf|David M. Zar 2016 Clock Domain Crossing Lecture]] | ||
| + | *[[media:Zar_Metastability_Lecture.pdf|David M. Zar Metastability Lecture 2012]] | ||
| + | *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] | ||
| + | |||
| + | *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] | ||
| + | *[[media:Asynchronous.pdf|Asynchronous Circuits]] | ||
| + | *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] | ||
| + | *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] | ||
| + | *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] | ||
| + | *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] | ||
| + | *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] | ||
| + | *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] | ||
| + | *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] | ||
| + | *[[media:AsynchArt.pdf|Asynchronous Design Methodologies: An Overview]] | ||
| + | |||
| + | |||
| + | ASYNCHRONOUS CPUs | ||
| + | |||
| + | http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU | ||
| + | |||
| + | http://en.wikipedia.org/wiki/ILLIAC_II | ||
| + | |||
| + | http://en.wikipedia.org/wiki/AMULET_microprocessor | ||
| + | |||
| + | http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf | ||
| + | |||
| + | *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] | ||
| + | |||
| + | |||
| + | VERIFICATION | ||
| + | |||
| + | *[[media:Test.pdf|Automatic Test Generation]] | ||
| + | *[[media:Fsmtest.pdf|Testing FSMs]] | ||
| + | *[[media:Bist.pdf|BIST]] | ||
Latest revision as of 20:32, 26 April 2016
LOGIC MINIMIZATION
- Standard Cell Example
- Karnaugh Maps
- Synthesis of Two-Level Circuits
- Quine-McCluskey Example
- UCP Reduction Techniques
http://en.wikipedia.org/wiki/Petrick%27s_method
- Don't Cares
- Multiple Output Functions
- Iterated Consensus
- Boole's Expansion Theorem
- Decomposition By Expansion
http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf
http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer
- Espresso Example (Quine-McCluskey Example)
- Espresso Example Output (Quine-McCluskey Example)
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- Espresso Arctan Bit 0 Example
- Espresso Arctan Bit 0 Example Output
http://www.mosis.com/pages/design/flows/design-flow-scmos-kits
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic Default Settings
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings
- VHDL Example 2 (Quine-McCluskey Example)
- VHDL Example 2 Synthesized RTL Schematic Default Settings
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings
- VHDL Example 3 (12-bit Arctan Function)
- VHDL Example 4 (12-bit Arctan Function MSB)
- VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)
- VHDL Example 5 (12-bit Arctan Function Bit 10)
- VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)
- VHDL Example 6 (12-bit Arctan Function Bit 9)
- VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)
- VHDL Example 7 (12-bit Arctan Function Bit 8)
- VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)
- VHDL Example 8 (12-bit Arctan Function Bit 0)
- VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)
- VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)
- VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)
- VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)
- VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)
- VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)
- VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)
- VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)
- VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)
- VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)
- Bit Zero Optimal LUTS (85 LUTs Is Optimal)
- Francis Paper
- Cong Optimality Paper
- Altera vs. Xilinx
- Xilinx vs. Altera
- Altera Logic Efficiency Analysis
- Altera FPGA Architecture White Paper
SEQUENTIAL SYSTEMS
- State Equal Output Moore Example
- State Equal Output Moore Example VHDL
- State Equal Output Moore Example Simulation
- State Equal Output Moore Example Synthesis Report Default Settings
- State Equal Output Moore Example Technology Map Schematic Default Settings
- ISE Screenshot: Generating Post Place-and-Route Simulation Model
- ISE Screenshot: Simulating Post Place-and-Route Simulation Model
- State Equal Output Moore Example Post Place-and-Route Simulation
- State Equal Output Moore Example Post Place-and-Route Simulation 2
- State Equal Output Moore Example 2 VHDL
- State Equal Output Moore Example 2 Simulation
- State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User
- State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User
- State Equal Output Moore Example 3 VHDL
- State Equal Output Moore Example 3 Simulation
- State Equal Output Moore Example 3 Synthesis Report Default Settings
- State Equal Output Moore Example 3 Technology Map Schematic Default Settings
- State Equal Output Moore Example 4 VHDL
- State Equal Output Moore Example 4 Simulation
- State Equal Output Moore Example 4 Synthesis Report Default Settings
- State Equal Output Moore Example 4 Technology Map Schematic Default Settings
- Figure 7.4 (4 States)
- Figure 7.4 VHDL Description Version 1
- Xilinx Spartan 6 Technology Map Schematic Default Settings
- Default Version 1 Synthesis Report
- Version 1 ModelSim Simulation
- Figure 7.4 VHDL Description Version 2
- Default Version 2 Synthesis Report
- Figure 7.4 VHDL Description Version 3
- Default Version 3 Synthesis Report
- Figure 7.4 (3 States)
- VHDL Description Version 4 (3 States)
- Version 4 ModelSim Simulation
- Default Version 4 Synthesis Report
- XST User Guide (See Page 276 for Compact State Encoding)
- Figure 7.4 (5 States)
- VHDL Description Version 5 (5 States)
- Default Version 5 Synthesis Report
- Definitions and Theorems for Sequential Machines
- Definition of Prime Compatible from Hachtel and Somenzi
- Minimizing Completely Specified Machines
- Simplification of Completely Specified Machines by Implication Tables
- Simplification of Incompletely Specified Machines
- Simplification of Incompletely Specified Machines 1
- Simplification of Incompletely Specified Machines 2
- Prime Compatibles Example from Hachtel and Somenzi (Revised)
- BCP Reduction Techniques
- State Assignment
ASYNCHRONOUS CIRCUITS AND METASTABILITY
- MX045 Oscillator Datasheet
- Oscillators and Clock Distribution
- How Fast Can We Clock A Circuit?
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
- Metastability
- David M. Zar 2016 Clock Domain Crossing Lecture
- David M. Zar Metastability Lecture 2012
- Cypress 2Kx9 Sync FIFO
- Introduction to Asynchronous Circuits
- Asynchronous Circuits
- Designing the SR Latch
- Designing an Asynchronous Counter
- Designing a Sequence Detector
- Kohavi Text Example
- Designing the Edge-Triggered D Flip-Flop
- The Reflected Binary (Gray) Code
- Essential Hazards in Asynchronous Sequential Machines
- Asynchronous Design Methodologies: An Overview
ASYNCHRONOUS CPUs
http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU
http://en.wikipedia.org/wiki/ILLIAC_II
http://en.wikipedia.org/wiki/AMULET_microprocessor
http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf
VERIFICATION
