Syllabus

FALL NEVER

LECTURE	DATE	TOPICS	PREPARATION	DUE	ASSIGNED
1	AUG 28	Course Introduction Classification of Computers and Instructions Addressing Modes	Course Introduction Chapter 1 Chapter 2
2	AUG 30	RISC vs. CISC The Really Simple RISC (RSRC) SRC Assembly Language	Chapter 2 The Case for the RISC David Patterson David Ditzel The Really Simple RISC Computer (update) The SRC/RSRC Instruction Set
3	SEPT 4	RSRC VHDL/FPGA Implementation	VHDL Tutorial RSRC Vivado Tutorial (update) Xilinx Vivado Clock Constraints Tutorial
4	SEPT 6	Microprogramming the SRC	Chapter 5 Microprogrammed SRC Control Unit Microprogrammed SRC CONTROL.VHD Microprogrammed SRC CONTROLSTORE.VHD Microcoded SRC VHDL Zip File Intel Software Developer's Manual (see pages 285, 339)
5	SEPT 11	1-Bus vs 2-Bus vs 3-Bus Microarchitecture Introduction to Pipelining	Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams Chapter 5 Basic Pipelined SRC
6	SEPT 13	Pipelining the SRC	Chapter 5 Table 5.1 Basic Pipelined SRC Pipelined SRC Execution Simulation Corrected Figure 5.15
7	SEPT 18	Pipelined RSRC VHDL/FPGA Implementation Interrupts/Exceptions	Chapter 4 Chapter 5
8	SEPT 20	Review
9	SEPT 25	Introduction to Memory Memory Space Decoding Introduction to Schematic Capture	Chapter 7 AM27C256 EPROM Datasheet EPROM Example CY7C199N SRAM Datasheet SRAM Example
10	SEPT 26	Exam 1
11	OCT 2	Memory DIMMs and Modules Introduction to Schematic	Chapter 7 ExpressSCH Quick Start Guide
12	OCT 4	FPM DRAM SRC FPM DRAM Design Examples	FPM DRAM Datasheet SRC FPM DRAM Design Examples
13	OCT 9	SDRAM DDR DRAM DDR2 DRAM DDR3 DRAM	DRAM Types MT48LC8M8A2 SDRAM Datasheet MT46V128M8 DDR DRAM Datasheet MT47H256M8 DDR2 DRAM Datasheet MT41J512M8 DDR3 DRAM Datasheet MT40A1G8 DDR4 DRAM DDR2 Core for Digilent NEXYS4DDR Board Xilinx DDR3 Core for 7 Series FPGAs
14	OCT 11	Cache Virtual Memory	Chapter 7 SRC Cache Example SRC Cache Datapath Example Intel Core i7 (Haswell) Cache Parameters Virtual Memory Concepts Virtual Memory H&P
	OCT 16	Fall Break
15	OCT 18	Memory-Mapped I/O Shared I/O Polling Interrupt-Driven I/O Direct Memory Access (DMA) The Multi-Master SRC Bus Bus Arbitration	Chapter 8 SRC Stereo Card Bus Alternatives SRC IN and OUT RTN Three-Slot Multi-Master SRC Motherboard
16	OCT 23	The PCI Bus	PCI Lecture Notes X86 Chipset Evolution
17	OCT 25	Serial vs. Parallel I/O Buses PCIe	LTSPICE Tutorial Reflection Lecture PCIe Lecture
18	OCT 30	Parity Hamming Codes ECC Memory	Chapter 8 Coding Theory 101 Hamming Codes PCIe CRC
19	NOV 1	Disks Video DACs ADCs	Chapter 9 SRC Video Example R2R DAC Example Flash ADC Example
20	NOV 6	USB 2.0/3.0 IEEE 1394 (Firewire)	Chapter 10 USB 2.0 Specification
21	NOV 8	Exam 2
22	NOV 13	Introduction to Pipelining	Chapter 5 The Case for RISC Basic Pipelined SRC
23	NOV 15	Pipelining the SRC	Chapter 5 Table 5.1 Pipelined SRC Execution Simulation Corrected Figure 5.15
24	NOV 20	Microprogramming the SRC	Chapter 5 Microprogrammed SRC Control Unit Microprogrammed SRC CONTROL.VHD Microprogrammed SRC CONTROLSTORE.VHD Microcoded SRC VHDL Zip File Intel Software Developer's Manual (see pages 285, 339)
	NOV 22	Thanksgiving Break
25	NOV 27	Very Long Instruction Word (VLIW) Computing Superscalar/Out-of-Order Processing 64-Bit Desktop Computing: AMD vs. Intel Explicitly Parallel Instruction Computing (EPIC)	CPU History Fisher Paper 1 Fisher Paper 2 VLIW Notes AMD K7 Presentation AMD Hammer Intel Intanium
26	NOV 29	Transmeta Crusoe Symmetric Multiprocessing (SMP) Simultaneous Multithreading (SMT) Introduction to Multicore/Cache Coherency →Global Directory →MESI (Snoopy/Pentium II) →MOESI (ccNUMA/AMD Hammer) →MESIF (ccNUMA/Intel Xeon Phi)	David Ditzel Transmeta Crusoe White Paper HP Transmeta Crusoe Laptop Intel Core i9 SPARC T5 Censier Paper Illinois Protocol Paper (1984) Intel Pentium II MESI Chipset AMD Hammer Intel Xeon Phi
27	DEC 4	Supercomputing	Top 500 FLOPS Longbottom's Linpack Page WUSTL CHPC CHPC Photo WUSTL SEAS Linux Lab Cluster
28	DEC 6	Exam 3