LECTURE
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DATE
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TOPICS
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PREPARATION
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DUE
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ASSIGNED
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1
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AUG 28
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Course Introduction Classification of Computers and Instructions Addressing Modes
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Course Introduction Chapter 1 Chapter 2
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2
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AUG 30
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RISC vs. CISC The Really Simple RISC Computer (RSRC) SRC/RSRC Assembly Language
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Chapter 2 The Case for the RISC David Patterson David Ditzel The Really Simple RISC Computer The SRC/RSRC Instruction Set
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3
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SEPT 4
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RSRC VHDL/FPGA Implementation
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VHDL Tutorial RSRC Vivado Tutorial Xilinx Vivado Clock Constraints Tutorial
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4
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SEPT 6
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Microprogramming the RSRC
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Chapter 5 Microprogrammed RSRC Control Unit Microprogrammed RSRC CONTROL.VHD (update) Microprogrammed RSRC CONTROLSTORE.VHD (update) Microcoded RSRC VHDL Zip File (update) Intel Software Developer's Manual (see pages 285, 339) Microprogrammed RSRC Control Unit Modified
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5
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SEPT 11
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1-Bus vs 2-Bus vs 3-Bus Microarchitecture Introduction to Pipelining
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Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams Chapter 5 Basic Pipelined SRC/RSRC
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6
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SEPT 13
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Pipelining the SRC/RSRC
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Chapter 5 Table 5.1 Basic Pipelined SRC/RSRC Corrected Figure 5.15
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7
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SEPT 18
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Pipelined SRC/RSRC VHDL/FPGA Implementation
Interrupts/Exceptions
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Chapter 5 Pipelined SRC/RSRC Execution Simulation Chapter 4
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8
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SEPT 20
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Review
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9
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SEPT 25
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Introduction to Memory Address Decoding
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Chapter 7 AM27C256 EPROM Datasheet EPROM Example CY7C199N SRAM Datasheet SRAM Example
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10
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SEPT 26
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Exam 1
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11
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OCT 2
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Memory DIMMs and Modules Introduction to Schematic Capture
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Chapter 7 ExpressSCH Quick Start Guide
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12
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OCT 4
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FPM DRAM SRC/RSRC FPM DRAM Design Examples
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FPM DRAM Datasheet SRC/RSRC FPM DRAM Design Examples
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13
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OCT 9
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SDRAM DDR DRAM DDR2 DRAM DDR3 DRAM
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DRAM Types MT48LC8M8A2 SDRAM Datasheet MT46V128M8 DDR DRAM Datasheet MT47H256M8 DDR2 DRAM Datasheet MT41J512M8 DDR3 DRAM Datasheet MT40A1G8 DDR4 DRAM DDR2 Core for Digilent NEXYS4DDR Board Xilinx DDR3 Core for 7 Series FPGAs
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14
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OCT 11
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Cache Virtual Memory
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Chapter 7 SRC/RSRC Cache Example SRC/RSRC Cache Datapath Example Intel Core i7 (Haswell) Cache Parameters Virtual Memory Concepts Virtual Memory H&P
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OCT 16
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Fall Break
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15
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OCT 18
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Memory-Mapped I/O Shared I/O Polling Interrupt-Driven I/O Direct Memory Access (DMA) The Multi-Master SRC Bus Bus Arbitration
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Chapter 8 SRC Stereo Card Bus Alternatives SRC IN and OUT RTN Three-Slot Multi-Master SRC Motherboard
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16
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OCT 23
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The PCI Bus
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PCI Lecture Notes X86 Chipset Evolution
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17
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OCT 25
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Serial vs. Parallel I/O Buses PCIe
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LTSPICE Tutorial Reflection Lecture PCIe Lecture
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18
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OCT 30
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Parity Hamming Codes ECC Memory
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Chapter 8 Coding Theory 101 Hamming Codes PCIe CRC
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19
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NOV 1
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Disks Video DACs ADCs
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Chapter 9 SRC Video Example R2R DAC Example Flash ADC Example
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20
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NOV 6
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USB 2.0/3.0 IEEE 1394 (Firewire)
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Chapter 10 USB 2.0 Specification
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21
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NOV 8
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Exam 2
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22
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NOV 13
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Very Long Instruction Word (VLIW) Computing Superscalar/Out-of-Order Processing
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CPU History Fisher Paper 1 Fisher Paper 2 VLIW Notes AMD K7 Presentation
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23
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NOV 15
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Explicitly Parallel Instruction Computing (EPIC) 64-Bit Desktop Computing: AMD vs. Intel
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Intel Intanium AMD Hammer
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24
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NOV 20
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Transmeta Crusoe
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David Ditzel Transmeta Crusoe White Paper HP Transmeta Crusoe Laptop
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NOV 22
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Thanksgiving Break
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25
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NOV 27
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Symmetric Multiprocessing (SMP) Simultaneous Multithreading (SMT) Introduction to Multicore/Cache Coherency →Global Directory →MESI (Snoopy/Pentium II) →MOESI (ccNUMA/AMD Hammer) →MESIF (ccNUMA/Intel Xeon Phi)
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Intel Core i9 SPARC T5 Censier Paper Illinois Protocol Paper (1984) Intel Pentium II MESI Chipset AMD Hammer Intel Xeon Phi
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26
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NOV 29
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Deep Dive: The Illinois Protocol (MESI)
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Illinois Protocol Paper (1984) Intel Pentium II MESI Chipset
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27
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DEC 4
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Supercomputing
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Top 500 FLOPS Longbottom's Linpack Page WUSTL CHPC CHPC Photo WUSTL SEAS Linux Lab Cluster
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28
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DEC 6
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Exam 3
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