Difference between revisions of "Syllabus"

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|OCT 10
 
|OCT 10
 
|SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM
 
|SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM
|[[media:DRAM_TYPES.pdf‎|DRAM Types]]<br />[[media:MT48LCM8A2.pdf‎|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf‎|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf‎|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf‎|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]
+
|[[media:DRAM_TYPES.pdf‎|DRAM Types]]<br />[[media:MT48LCM8A2.pdf‎|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf‎|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf‎|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf‎|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs]
 
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Revision as of 15:00, 10 October 2017

FALL 2017
LECTURE DATE TOPICS PREPARATION DUE ASSIGNED
1 AUG 29 Course Introduction
Classification of Computers and Instructions
Course Introduction
Chapter 1
Chapter 2
2 AUG 31 Addressing Modes
RISC vs. CISC
The Simple RISC (SRC)
SRC Assembly Language
Chapter 2
The Case for the RISC
Homework 1
3 SEPT 5 SRC Abstract RTN
Displacement-Based Addressing
Chapter 2
SRC Abstract RTN
Displacement-Based Addressing
4 SEPT 7 1-Bus SRC Microarchitecture
1-Bus SRC Concrete RTN
Chapter 4
1-Bus SRC Block Diagrams
1-Bus SRC RTN
Homework 1 Homework 2
5 SEPT 12 1-Bus SRC Control FSM
2-Bus SRC Microarchitecture
3-Bus SRC Microarchitecture
Chapter 4
2-Bus SRC Block Diagrams
3-Bus SRC Block Diagrams
6 SEPT 14 SRC VHDL Implementation VHDL Tutorial
1-Bus SRC VHDL
Homework 2 Homework 3
7 SEPT 19 SRC FPGA Implementation 1-BUS SRC Vivado Tutorial
Vivado Clock Constraint Tutorial
8 SEPT 21 Interrupts/Exceptions Chapter 4 Homework 3
9 SEPT 26 Exam 1 Results
10 SEPT 28 Introduction to Memory
Memory Space Decoding
Introduction to Schematic Capture
Chapter 7
AM27C256 EPROM Datasheet
EPROM Example
CY7C199N SRAM Datasheet
SRAM Example
Homework 4
11 OCT 3 Schematic Capture Details
Memory Boards and Modules
Chapter 7
ExpressSCH Quick Start Guide
12 OCT 5 FPM DRAM
SRC FPM DRAM Design Examples
FPM DRAM Datasheet
SRC FPM DRAM Design Examples
Homework 4 Homework 5
13 OCT 10 SDRAM
DDR DRAM
DDR2 DRAM
DDR3 DRAM
DRAM Types
MT48LC8M8A2 SDRAM Datasheet
MT46V128M8 DDR DRAM Datasheet
MT47H256M8 DDR2 DRAM Datasheet
MT41J512M8 DDR3 DRAM Datasheet
MT40A1G8 DDR4 DRAM
DDR2 Core for Digilent NEXYS4DDR Board
Xilinx DDR3 Core for 7 Series FPGAs
14 OCT 12 Cache
Virtual Memory
Chapter 7
SRC Cache Example
SRC Cache Datapath Example
Virtual Memory Concepts
Homework 5 Homework 6
OCT 17 Fall Break
15 OCT 19 Memory-Mapped I/O
Shared I/O
Polling
Interrupt-Driven I/O
Direct Memory Access (DMA)
The Multi-Master SRC Bus
Bus Arbitration
Chapter 8
SRC Stereo Card Bus Alternatives
Three-Slot Multi-Master SRC Motherboard
Homework 6 Homework 7
16 OCT 24 The PCI Bus PCI Lecture Notes
17 OCT 26 Serial vs. Parallel I/O Buses
PCIe
LTSPICE Tutorial
Reflection Lecture
PCIe Lecture
Homework 7 Homework 8
18 OCT 31 Parity
Hamming Codes
ECC Memory
Chapter 8
Coding Theory 101
19 NOV 2 Disks
Video
DACs
ADCs
Chapter 9
SRC Video Example
R2R DAC Example
Flash ADC Example
Homework 8
20 NOV 7 USB 2.0/3.0
IEEE 1394 (Firewire)
Chapter 10
21 NOV 9 Exam 2
22 NOV 14 Introduction to Pipelining Chapter 5 Homework 9
23 NOV 16 Pipelining the SRC Chapter 5
Pipelined SRC Execution Simulation
24 NOV 21 Microprogramming the SRC Chapter 5
Microprogrammed SRC Control Unit
Microprogrammed SRC CONTROL.VHD
Microprogrammed SRC CONTROLSTORE.VHD
Homework 9 Homework 10
NOV 23 Thanksgiving Break
25 NOV 28 Very Long Instruction Word (VLIW) Computing
Superscalar/Out-of-Order Processing
Explicitly Parallel Instruction Computing (EPIC)
Chapter 5
Fisher Paper 1
Fisher Paper 2
VLIW Notes
AMD K7 Presentation
Intel Intanium
26 NOV 30 Transmeta Crusoe
Introduction to Multicore/Cache Coherency
Transmeta Crusoe White Paper
Illinois Protocol Paper (1984)
Homework 10
27 DEC 5 Supercomputing
28 DEC 7 Exam 3