Difference between revisions of "Syllabus"
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|Memory DIMMs and Modules<br />Introduction to Schematic Capture | |Memory DIMMs and Modules<br />Introduction to Schematic Capture | ||
|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]] | ||
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|[[media:DRAM_TYPES.pdf|DRAM Types]]<br />[[media:MT48LCM8A2.pdf|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs] | |[[media:DRAM_TYPES.pdf|DRAM Types]]<br />[[media:MT48LCM8A2.pdf|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs] | ||
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|Cache<br />Virtual Memory | |Cache<br />Virtual Memory | ||
|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC/RSRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC/RSRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC/RSRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC/RSRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] | ||
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|Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | |Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | ||
|[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | |[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | ||
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|[[media:PCI_Lecture.pdf|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]] | |[[media:PCI_Lecture.pdf|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]] | ||
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|Serial vs. Parallel I/O Buses<br />PCIe | |Serial vs. Parallel I/O Buses<br />PCIe | ||
|[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | |[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | ||
− | | | + | |Homework 6 |
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|[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | |[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | ||
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|[[media:Ch10CSDA.pdf|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]] | |[[media:Ch10CSDA.pdf|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]] | ||
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+ | |Lab 3 | ||
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