Difference between revisions of "Syllabus"

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{| class="wikitable"
 
{| class="wikitable"
|+FALL 2017
+
|+FALL 2018
 
|-
 
|-
 
|LECTURE
 
|LECTURE
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|TOPICS
 
|TOPICS
 
|PREPARATION
 
|PREPARATION
 +
|ASSIGNED
 
|DUE
 
|DUE
|ASSIGNED
 
  
 
|-
 
|-
 
|1
 
|1
|AUG 29
+
|AUG 28
|Course Introduction<br />Classification of Computers and Instructions
+
|Course Introduction<br />Classification of Computers and Instructions<br />Addressing Modes
 
|[[media:Day_1.pdf‎|Course Introduction]]<br />[[media:Ch1CSDA.pdf‎|Chapter 1]]<br />[[media:Ch2CSDA.pdf‎|Chapter 2]]
 
|[[media:Day_1.pdf‎|Course Introduction]]<br />[[media:Ch1CSDA.pdf‎|Chapter 1]]<br />[[media:Ch2CSDA.pdf‎|Chapter 2]]
|
+
|Homework 1
 
|
 
|
  
 
|-
 
|-
 
|2
 
|2
|AUG 31
+
|AUG 30
|Addressing Modes<br />RISC vs. CISC<br />The Simple RISC (SRC)<br />SRC Assembly Language
+
|RISC vs. CISC<br />The Really Simple RISC Computer (RSRC)<br />SRC/RSRC Assembly Language
|[[media:Ch2CSDA.pdf‎|Chapter 2]]<br />[[media:RISC.pdf‎|The Case for the RISC]]
+
|[[media:Ch2CSDA.pdf‎|Chapter 2]]<br />[[media:RISC.pdf‎|The Case for the RISC]]<br />[https://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) David Patterson]<br />[https://www.ece.iastate.edu/profiles/david-ditzel/ David Ditzel]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The SRC/RSRC Instruction Set]]
 
|
 
|
 +
|
 +
 +
|-
 +
|3
 +
|SEPT 4
 +
|RSRC VHDL/FPGA Implementation
 +
|[[media:EVERYTHING_YOU_ALWAYS_WANTED.PDF|VHDL Tutorial]]<br />[[media:RSRC_Vivado_Tutorial.pdf|RSRC Vivado Tutorial]]<br />[https://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Xilinx Vivado Clock Constraints Tutorial]
 +
|Homework 2
 
|Homework 1
 
|Homework 1
  
 
|-
 
|-
|3
+
|4
|SEPT 5
+
|SEPT 6
|SRC Abstract RTN<br />Displacement-Based Addressing
+
|Introduction to Memory<br />Address Decoding<br />Xilinx IP Cores<br />&rarr;Xilinx FPGA Block RAM<br />&rarr;Xilinx Digital Clock Manager (DCM)
|[[media:Ch2CSDA.pdf‎|Chapter 2]]<br />[[media:SRC_RTN.pdf‎|SRC Abstract RTN]]<br />[[media:DISPLACEMENT.pdf‎|Displacement-Based Addressing]]
+
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:Am27c256.pdf‎|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf‎|EPROM Example]]<br />[[media:Cy7c199n_8.pdf‎|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf‎|SRAM Example]]
 
|
 
|
 
|
 
|
 +
  
 
|-
 
|-
|4
+
|5
|SEPT 7
+
|SEPT 11
|1-Bus SRC Microarchitecture<br />1-Bus SRC Concrete RTN
+
|Microprogramming the RSRC
|[[media:Ch4WDR.pdf‎|Chapter 4]]<br />[[media:1-Bus_Block_Diagrams.pdf‎|1-Bus SRC Block Diagrams]]<br />[[media:1busrtn.pdf |1-Bus SRC RTN]]
+
|[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:Microprogrammed_RSRC_Control_Unit.pdf‎|Microprogrammed RSRC Control Unit]]<br />[[media:Control.pdf‎|Microprogrammed RSRC CONTROL.VHD]]<br />[[media:Controlstore.pdf‎|Microprogrammed RSRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded RSRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]]<br />[[media:Microprogrammed_RSRC_Control_Unit_Modifed.pdf|Microprogrammed RSRC Control Unit Modified]]
|Homework 1
+
|Lab 1
 
|Homework 2
 
|Homework 2
  
 
|-
 
|-
|5
+
|6
|SEPT 12
+
|SEPT 13
|1-Bus SRC Control FSM<br />2-Bus SRC Microarchitecture<br />3-Bus SRC Microarchitecture
+
|1-Bus vs 2-Bus vs 3-Bus Microarchitecture<br />Introduction to Pipelining
|[[media:Ch4WDR.pdf‎|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf‎|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf‎|3-Bus SRC Block Diagrams]]
+
|[[media:Ch4WDR.pdf‎|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf‎|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf‎|3-Bus SRC Block Diagrams]]<br />[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC/RSRC]]
 
|
 
|
 
|
 
|
  
 
|-
 
|-
|6
+
|7
|SEPT 14
+
|SEPT 18
|SRC VHDL Implementation
+
|Pipelining the SRC/RSRC
|[[media:EVERYTHING_YOU_ALWAYS_WANTED.PDF|VHDL Tutorial]]<br />[[media:Srcvhdl.zip‎|1-Bus SRC VHDL]]
+
|[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:Table_5P1.pdf|Table 5.1]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC/RSRC]]<br />[[media:Corrected_Figure_5.15.pdf|Corrected Figure 5.15]]
|Homework 2
 
 
|Homework 3
 
|Homework 3
 
|-
 
|7
 
|SEPT 19
 
|SRC FPGA Implementation
 
|[[media:Vivado_Simulation_Tutorial.pdf|1-BUS SRC Vivado Tutorial]]<br />[https://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraint Tutorial]
 
|
 
 
|
 
|
  
 
|-
 
|-
 
|8
 
|8
|SEPT 21
+
|SEPT 20
|Interrupts/Exceptions
+
|Pipelined SRC/RSRC VHDL/FPGA Implementation<br /><br />Interrupts/Exceptions
|[[media:Ch4WDR.pdf‎|Chapter 4]]
+
|[[media:Ch5CSDA.pdf‎|Chapter 5]]<br />[[media:Pipelined_SRC.pdf‎|Pipelined SRC/RSRC Execution Simulation]]<br />[[media:Ch4WDR.pdf‎|Chapter 4]]
|Homework 3
+
|
 
|
 
|
  
 
|-
 
|-
 
|9
 
|9
|SEPT 26
+
|SEPT 25
|Exam 1
+
|Review
|
 
 
|
 
|
 
|
 
|
 +
|Homework 3<br />Lab 1
  
 
|-
 
|-
 
|10
 
|10
|SEPT 28
+
|SEPT 27
|Introduction to Memory<br />Memory Space Decoding<br />Introduction to Schematic Capture
+
|Exam 1
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:Am27c256.pdf‎|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf‎|EPROM Example]]<br />[[media:Cy7c199n_8.pdf‎|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf‎|SRAM Example]]
+
|
 +
|
 
|
 
|
|Homework 4
 
  
 
|-
 
|-
 
|11
 
|11
|OCT 3
+
|OCT 2
|Schematic Capture Details<br />Memory Boards and Modules
+
|Memory DIMMs and Modules<br />Introduction to Schematic Capture
 
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]]
 
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]]
|
+
|Homework 4<br />Lab 2
 
|
 
|
  
 
|-
 
|-
 
|12
 
|12
|OCT 5
+
|OCT 4
|FPM DRAM<br />SRC FPM DRAM Design Examples
+
|FPM DRAM<br />SRC/RSRC FPM DRAM Design Examples
|[[media:MT4LC8M8B6.pdf‎|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC FPM DRAM Design Examples]]
+
|[[media:MT4LC8M8B6.pdf‎|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC/RSRC FPM DRAM Design Examples]]
|Homework 4
+
|
|Homework 5
+
|
  
 
|-
 
|-
 
|13
 
|13
|OCT 10
+
|OCT 9
 
|SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM
 
|SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM
 
|[[media:DRAM_TYPES.pdf‎|DRAM Types]]<br />[[media:MT48LCM8A2.pdf‎|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf‎|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf‎|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf‎|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs]
 
|[[media:DRAM_TYPES.pdf‎|DRAM Types]]<br />[[media:MT48LCM8A2.pdf‎|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf‎|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf‎|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf‎|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs]
 
|
 
|
|
+
|Homework 4
  
 
|-
 
|-
 
|14
 
|14
|OCT 12
+
|OCT 11
 
|Cache<br />Virtual Memory
 
|Cache<br />Virtual Memory
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:Cache_Example.pdf‎|SRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf‎|SRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf‎|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]]
+
|[[media:Ch7CSDA.pdf‎|Chapter 7]]<br />[[media:Cache_Example.pdf‎|SRC/RSRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf‎|SRC/RSRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf‎|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]]
 
|Homework 5
 
|Homework 5
|Homework 6
+
|
  
 
|-
 
|-
 
|
 
|
|OCT 17
+
|OCT 16
 
|Fall Break
 
|Fall Break
 
|
 
|
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|-
 
|-
 
|15
 
|15
|OCT 19
+
|OCT 18
 
|Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration
 
|Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration
 
|[[media:Ch8CSDA.pdf‎|Chapter 8]]<br />[[media:Stereo.pdf‎|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf‎|Three-Slot Multi-Master SRC Motherboard]]
 
|[[media:Ch8CSDA.pdf‎|Chapter 8]]<br />[[media:Stereo.pdf‎|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf‎|Three-Slot Multi-Master SRC Motherboard]]
|Homework 6
+
|Lab 3
|Homework 7
+
|Lab 2
  
 
|-
 
|-
 
|16
 
|16
|OCT 24
+
|OCT 23
 
|The PCI Bus
 
|The PCI Bus
 
|[[media:PCI_Lecture.pdf‎|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]]
 
|[[media:PCI_Lecture.pdf‎|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]]
 
|
 
|
|
+
|Homework 5
  
 
|-
 
|-
 
|17
 
|17
|OCT 26
+
|OCT 25
 
|Serial vs. Parallel I/O Buses<br />PCIe
 
|Serial vs. Parallel I/O Buses<br />PCIe
 
|[[media:LTSPICE_TUTORIAL.pdf‎|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf‎|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf‎|PCIe Lecture]]
 
|[[media:LTSPICE_TUTORIAL.pdf‎|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf‎|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf‎|PCIe Lecture]]
|Homework 7
+
|Homework 6
|Homework 8
+
|
  
 
|-
 
|-
 
|18
 
|18
|OCT 31
+
|OCT 30
 
|Parity<br />Hamming Codes<br />ECC Memory
 
|Parity<br />Hamming Codes<br />ECC Memory
 
|[[media:Ch8CSDA.pdf‎|Chapter 8]]<br />[[media:Coding_Theory_001.pdf‎|Coding Theory 101]]<br />[[media:Hamming_Code_Example_With_Odd_Parity.pdf|Hamming Codes]]<br />[http://www.verien.com/pcie_primer.htm PCIe CRC]
 
|[[media:Ch8CSDA.pdf‎|Chapter 8]]<br />[[media:Coding_Theory_001.pdf‎|Coding Theory 101]]<br />[[media:Hamming_Code_Example_With_Odd_Parity.pdf|Hamming Codes]]<br />[http://www.verien.com/pcie_primer.htm PCIe CRC]
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|-
 
|-
 
|19
 
|19
|NOV 2
+
|NOV 1
 
|Disks<br />Video<br />DACs<br />ADCs
 
|Disks<br />Video<br />DACs<br />ADCs
 
|[[media:Ch9CSDA.pdf‎|Chapter 9]]<br />[[media:Video_Example.pdf‎|SRC Video Example]]<br />[[media:R2R_DAC.pdf‎|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]]
 
|[[media:Ch9CSDA.pdf‎|Chapter 9]]<br />[[media:Video_Example.pdf‎|SRC Video Example]]<br />[[media:R2R_DAC.pdf‎|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]]
|Homework 8
 
 
|
 
|
 +
|Homework 6
  
 
|-
 
|-
 
|20
 
|20
|NOV 7
+
|NOV 6
 
|USB 2.0/3.0<br />IEEE 1394 (Firewire)
 
|USB 2.0/3.0<br />IEEE 1394 (Firewire)
 
|[[media:Ch10CSDA.pdf‎|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]]
 
|[[media:Ch10CSDA.pdf‎|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]]
 
|
 
|
 +
|Lab 3
  
 
|-
 
|-
 
|21
 
|21
|NOV 9
+
|NOV 8
 
|Exam 2
 
|Exam 2
 
|
 
|
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|-
 
|-
 
|22
 
|22
|NOV 14
+
|NOV 13
|Introduction to Pipelining
+
|Very Long Instruction Word (VLIW) Computing<br />Superscalar/Out-of-Order Processing
|[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:RISC.pdf|The Case for RISC]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC]]
+
|[[media:CPU History.pdf|CPU History]]<br />[[media:Fisher_Paper_1.pdf‎|Fisher Paper 1]]<br />[[media:Fisher_Paper_2.pdf‎|Fisher Paper 2]]<br />[[media:VLIW.pdf‎|VLIW Notes]]<br />[[media:K7pres.pdf‎|AMD K7 Presentation]]
|Homework 9
+
|
 
|
 
|
  
 
|-
 
|-
 
|23
 
|23
|NOV 16
+
|NOV 15
|Pipelining the SRC
+
|Explicitly Parallel Instruction Computing (EPIC)<br />64-Bit Desktop Computing: AMD vs. Intel
|[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:Table_5P1.pdf|Table 5.1]]<br />[[media:Pipelined_SRC.pdf‎|Pipelined SRC Execution Simulation]]<br />[[media:Corrected_Figure_5.15.pdf|Corrected Figure 5.15]]
+
|[[media:Itanium.ua_ovw.pdf‎|Intel Intanium]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]
 
|
 
|
 
|
 
|
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|-
 
|-
 
|24
 
|24
|NOV 21
+
|NOV 20
|Microprogramming the SRC
+
|Transmeta Crusoe
|[[media:Ch5CSDA.pdf‎‎|Chapter 5]]<br />[[media:Microprogrammed_SRC_Control_Unit.pdf‎|Microprogrammed SRC Control Unit]]<br />[[media:Control.pdf‎|Microprogrammed SRC CONTROL.VHD]]<br />[[media:Controlstore.pdf‎|Microprogrammed SRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded SRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]]
+
|[https://www.ece.iastate.edu/profiles/david-ditzel David Ditzel]<br />[[media:Paper_aklaiber_19jan00.pdf‎|Transmeta Crusoe White Paper]]<br />[[media:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop]]
|Homework 9
+
|
|Homework 10
+
|
  
 
|-
 
|-
 
|
 
|
|NOV 23
+
|NOV 22
 
|Thanksgiving Break
 
|Thanksgiving Break
 
|
 
|
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|-
 
|-
 
|25
 
|25
|NOV 28
+
|NOV 27
|Very Long Instruction Word (VLIW) Computing<br />Superscalar/Out-of-Order Processing<br />64-Bit Desktop Computing: AMD vs. Intel<br />Explicitly Parallel Instruction Computing (EPIC)
+
|Symmetric Multiprocessing (SMP)<br />Simultaneous Multithreading (SMT)<br />Introduction to Multicore/Cache Coherency<br />&rarr;Global Directory<br />&rarr;MESI (Snoopy/Pentium II)<br />&rarr;MOESI (ccNUMA/AMD Hammer)<br />&rarr;MESIF (ccNUMA/Intel Xeon Phi)
|[[media:CPU History.pdf|CPU History]]<br />[[media:Fisher_Paper_1.pdf‎|Fisher Paper 1]]<br />[[media:Fisher_Paper_2.pdf‎|Fisher Paper 2]]<br />[[media:VLIW.pdf‎|VLIW Notes]]<br />[[media:K7pres.pdf‎|AMD K7 Presentation]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]<br />[[media:Itanium.ua_ovw.pdf‎|Intel Intanium]]
+
|[[media:Intel-core-x-series-processor-overview.pdf|Intel Core i9]]<br />[[media:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5]]<br />[[media:01675013.pdf|Censier Paper]]<br />[[media:Papamarcos.isca84.pdf‎|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]<br />[[media:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi]]
 
|
 
|
 
|
 
|
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|-
 
|-
 
|26
 
|26
|NOV 30
+
|NOV 29
|Transmeta Crusoe<br />Symmetric Multiprocessing (SMP)<br />Simultaneous Multithreading (SMT)<br />Introduction to Multicore/Cache Coherency<br />:Global Directory<br />:MESI<br />:MOESI
+
|Deep Dive: The Illinois Protocol (MESI)
|[https://www.ece.iastate.edu/profiles/david-ditzel David Ditzel]<br />[[media:Paper_aklaiber_19jan00.pdf‎|Transmeta Crusoe White Paper]]<br />[[media:Intel-core-x-series-processor-overview.pdf|Intel Core i9]]<br />[[media:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5]]<br />[[media:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi]]<br />[[media:Papamarcos.isca84.pdf‎|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Pentium II MESI Chipset]]
+
|[[media:Papamarcos.isca84.pdf‎|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]]
|Homework 10
+
|
 
|
 
|
  
 
|-
 
|-
 
|27
 
|27
|DEC 5
+
|DEC 4
 
|Supercomputing
 
|Supercomputing
|
+
|[https://en.wikipedia.org/wiki/TOP500 Top 500]<br />[https://en.wikipedia.org/wiki/FLOPS FLOPS]<br />[http://www.roylongbottom.org.uk/linpack%20results.htm Longbottom's Linpack Page]<br /n>[https://www.mir.wustl.edu/research/research-support-facilities/center-for-high-performance-computing-chpc WUSTL CHPC]<br />[https://source.wustl.edu/2017/12/view-12-4-17/#jp-carousel-245238 CHPC Photo]<br />[http://clusters.engineering.wustl.edu/index.php/Lab_Cluster WUSTL SEAS Linux Lab Cluster]
 
|
 
|
 
|
 
|
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|-
 
|-
 
|28
 
|28
|DEC 7
+
|DEC 6
|[[media:Exam_3_Supplemental_Material.pdf|Exam 3]]
+
|Exam 3
 
|
 
|
 
|
 
|

Latest revision as of 18:13, 12 September 2018

FALL 2018
LECTURE DATE TOPICS PREPARATION ASSIGNED DUE
1 AUG 28 Course Introduction
Classification of Computers and Instructions
Addressing Modes
Course Introduction
Chapter 1
Chapter 2
Homework 1
2 AUG 30 RISC vs. CISC
The Really Simple RISC Computer (RSRC)
SRC/RSRC Assembly Language
Chapter 2
The Case for the RISC
David Patterson
David Ditzel
The Really Simple RISC Computer
The SRC/RSRC Instruction Set
3 SEPT 4 RSRC VHDL/FPGA Implementation VHDL Tutorial
RSRC Vivado Tutorial
Xilinx Vivado Clock Constraints Tutorial
Homework 2 Homework 1
4 SEPT 6 Introduction to Memory
Address Decoding
Xilinx IP Cores
→Xilinx FPGA Block RAM
→Xilinx Digital Clock Manager (DCM)
Chapter 7
AM27C256 EPROM Datasheet
EPROM Example
CY7C199N SRAM Datasheet
SRAM Example


5 SEPT 11 Microprogramming the RSRC Chapter 5
Microprogrammed RSRC Control Unit
Microprogrammed RSRC CONTROL.VHD
Microprogrammed RSRC CONTROLSTORE.VHD
Microcoded RSRC VHDL Zip File
Intel Software Developer's Manual (see pages 285, 339)
Microprogrammed RSRC Control Unit Modified
Lab 1 Homework 2
6 SEPT 13 1-Bus vs 2-Bus vs 3-Bus Microarchitecture
Introduction to Pipelining
Chapter 4
2-Bus SRC Block Diagrams
3-Bus SRC Block Diagrams
Chapter 5
Basic Pipelined SRC/RSRC
7 SEPT 18 Pipelining the SRC/RSRC Chapter 5
Table 5.1
Basic Pipelined SRC/RSRC
Corrected Figure 5.15
Homework 3
8 SEPT 20 Pipelined SRC/RSRC VHDL/FPGA Implementation

Interrupts/Exceptions
Chapter 5
Pipelined SRC/RSRC Execution Simulation
Chapter 4
9 SEPT 25 Review Homework 3
Lab 1
10 SEPT 27 Exam 1
11 OCT 2 Memory DIMMs and Modules
Introduction to Schematic Capture
Chapter 7
ExpressSCH Quick Start Guide
Homework 4
Lab 2
12 OCT 4 FPM DRAM
SRC/RSRC FPM DRAM Design Examples
FPM DRAM Datasheet
SRC/RSRC FPM DRAM Design Examples
13 OCT 9 SDRAM
DDR DRAM
DDR2 DRAM
DDR3 DRAM
DRAM Types
MT48LC8M8A2 SDRAM Datasheet
MT46V128M8 DDR DRAM Datasheet
MT47H256M8 DDR2 DRAM Datasheet
MT41J512M8 DDR3 DRAM Datasheet
MT40A1G8 DDR4 DRAM
DDR2 Core for Digilent NEXYS4DDR Board
Xilinx DDR3 Core for 7 Series FPGAs
Homework 4
14 OCT 11 Cache
Virtual Memory
Chapter 7
SRC/RSRC Cache Example
SRC/RSRC Cache Datapath Example
Intel Core i7 (Haswell) Cache Parameters
Virtual Memory Concepts
Virtual Memory H&P
Homework 5
OCT 16 Fall Break
15 OCT 18 Memory-Mapped I/O
Shared I/O
Polling
Interrupt-Driven I/O
Direct Memory Access (DMA)
The Multi-Master SRC Bus
Bus Arbitration
Chapter 8
SRC Stereo Card Bus Alternatives
SRC IN and OUT RTN
Three-Slot Multi-Master SRC Motherboard
Lab 3 Lab 2
16 OCT 23 The PCI Bus PCI Lecture Notes
X86 Chipset Evolution
Homework 5
17 OCT 25 Serial vs. Parallel I/O Buses
PCIe
LTSPICE Tutorial
Reflection Lecture
PCIe Lecture
Homework 6
18 OCT 30 Parity
Hamming Codes
ECC Memory
Chapter 8
Coding Theory 101
Hamming Codes
PCIe CRC
19 NOV 1 Disks
Video
DACs
ADCs
Chapter 9
SRC Video Example
R2R DAC Example
Flash ADC Example
Homework 6
20 NOV 6 USB 2.0/3.0
IEEE 1394 (Firewire)
Chapter 10
USB 2.0 Specification
Lab 3
21 NOV 8 Exam 2
22 NOV 13 Very Long Instruction Word (VLIW) Computing
Superscalar/Out-of-Order Processing
CPU History
Fisher Paper 1
Fisher Paper 2
VLIW Notes
AMD K7 Presentation
23 NOV 15 Explicitly Parallel Instruction Computing (EPIC)
64-Bit Desktop Computing: AMD vs. Intel
Intel Intanium
AMD Hammer
24 NOV 20 Transmeta Crusoe David Ditzel
Transmeta Crusoe White Paper
HP Transmeta Crusoe Laptop
NOV 22 Thanksgiving Break
25 NOV 27 Symmetric Multiprocessing (SMP)
Simultaneous Multithreading (SMT)
Introduction to Multicore/Cache Coherency
→Global Directory
→MESI (Snoopy/Pentium II)
→MOESI (ccNUMA/AMD Hammer)
→MESIF (ccNUMA/Intel Xeon Phi)
Intel Core i9
SPARC T5
Censier Paper
Illinois Protocol Paper (1984)
Intel Pentium II MESI Chipset
AMD Hammer
Intel Xeon Phi
26 NOV 29 Deep Dive: The Illinois Protocol (MESI) Illinois Protocol Paper (1984)
Intel Pentium II MESI Chipset
27 DEC 4 Supercomputing Top 500
FLOPS
Longbottom's Linpack Page
WUSTL CHPC
CHPC Photo
WUSTL SEAS Linux Lab Cluster
28 DEC 6 Exam 3