Difference between revisions of "Syllabus"
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{| class="wikitable" | {| class="wikitable" | ||
− | |+FALL | + | |+FALL 2018 |
|- | |- | ||
|LECTURE | |LECTURE | ||
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|TOPICS | |TOPICS | ||
|PREPARATION | |PREPARATION | ||
+ | |ASSIGNED | ||
|DUE | |DUE | ||
− | |||
|- | |- | ||
|1 | |1 | ||
− | |AUG | + | |AUG 28 |
− | |Course Introduction<br />Classification of Computers and Instructions | + | |Course Introduction<br />Classification of Computers and Instructions<br />Addressing Modes |
|[[media:Day_1.pdf|Course Introduction]]<br />[[media:Ch1CSDA.pdf|Chapter 1]]<br />[[media:Ch2CSDA.pdf|Chapter 2]] | |[[media:Day_1.pdf|Course Introduction]]<br />[[media:Ch1CSDA.pdf|Chapter 1]]<br />[[media:Ch2CSDA.pdf|Chapter 2]] | ||
− | | | + | |Homework 1 |
| | | | ||
|- | |- | ||
|2 | |2 | ||
− | |AUG | + | |AUG 30 |
− | | | + | |RISC vs. CISC<br />The Really Simple RISC Computer (RSRC)<br />SRC/RSRC Assembly Language |
− | |[[media:Ch2CSDA.pdf|Chapter 2]]<br />[[media:RISC.pdf|The Case for the RISC]] | + | |[[media:Ch2CSDA.pdf|Chapter 2]]<br />[[media:RISC.pdf|The Case for the RISC]]<br />[https://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) David Patterson]<br />[https://www.ece.iastate.edu/profiles/david-ditzel/ David Ditzel]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The SRC/RSRC Instruction Set]] |
| | | | ||
+ | | | ||
+ | |||
+ | |- | ||
+ | |3 | ||
+ | |SEPT 4 | ||
+ | |RSRC VHDL/FPGA Implementation | ||
+ | |[[media:EVERYTHING_YOU_ALWAYS_WANTED.PDF|VHDL Tutorial]]<br />[[media:RSRC_Vivado_Tutorial.pdf|RSRC Vivado Tutorial]]<br />[https://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Xilinx Vivado Clock Constraints Tutorial] | ||
+ | |Homework 2 | ||
|Homework 1 | |Homework 1 | ||
|- | |- | ||
− | | | + | |4 |
− | |SEPT | + | |SEPT 6 |
− | | | + | |Introduction to Memory<br />Address Decoding<br />Xilinx IP Cores<br />→Xilinx FPGA Block RAM<br />→Xilinx Digital Clock Manager (DCM) |
− | |[[media: | + | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Am27c256.pdf|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:Cy7c199n_8.pdf|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf|SRAM Example]] |
| | | | ||
| | | | ||
+ | |||
|- | |- | ||
− | | | + | |5 |
− | |SEPT | + | |SEPT 11 |
− | | | + | |Microprogramming the RSRC |
− | |[[media: | + | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Microprogrammed_RSRC_Control_Unit.pdf|Microprogrammed RSRC Control Unit]]<br />[[media:Control.pdf|Microprogrammed RSRC CONTROL.VHD]]<br />[[media:Controlstore.pdf|Microprogrammed RSRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded RSRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]]<br />[[media:Microprogrammed_RSRC_Control_Unit_Modifed.pdf|Microprogrammed RSRC Control Unit Modified]] |
− | | | + | |Lab 1 |
|Homework 2 | |Homework 2 | ||
|- | |- | ||
− | | | + | |6 |
− | |SEPT | + | |SEPT 13 |
− | |1-Bus | + | |1-Bus vs 2-Bus vs 3-Bus Microarchitecture<br />Introduction to Pipelining |
− | |[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf|3-Bus SRC Block Diagrams]] | + | |[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf|3-Bus SRC Block Diagrams]]<br />[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC/RSRC]] |
| | | | ||
| | | | ||
|- | |- | ||
− | | | + | |7 |
− | |SEPT | + | |SEPT 18 |
− | |SRC | + | |Pipelining the SRC/RSRC |
− | |[[media: | + | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Table_5P1.pdf|Table 5.1]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC/RSRC]]<br />[[media:Corrected_Figure_5.15.pdf|Corrected Figure 5.15]] |
− | | | ||
|Homework 3 | |Homework 3 | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
| | | | ||
|- | |- | ||
|8 | |8 | ||
− | |SEPT | + | |SEPT 20 |
− | |Interrupts/Exceptions | + | |Pipelined SRC/RSRC VHDL/FPGA Implementation<br /><br />Interrupts/Exceptions |
− | |[[media:Ch4WDR.pdf|Chapter 4]] | + | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Pipelined_SRC.pdf|Pipelined SRC/RSRC Execution Simulation]]<br />[[media:Ch4WDR.pdf|Chapter 4]] |
− | | | + | | |
| | | | ||
|- | |- | ||
|9 | |9 | ||
− | |SEPT | + | |SEPT 25 |
− | + | |Review | |
− | | | ||
| | | | ||
| | | | ||
+ | |Homework 3<br />Lab 1 | ||
|- | |- | ||
|10 | |10 | ||
− | |SEPT | + | |SEPT 27 |
− | | | + | |Exam 1 |
− | | | + | | |
+ | | | ||
| | | | ||
− | |||
|- | |- | ||
|11 | |11 | ||
− | |OCT | + | |OCT 2 |
− | | | + | |Memory DIMMs and Modules<br />Introduction to Schematic Capture |
|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:ExpressSCH_Quick_Start_Guide.pdf|ExpressSCH Quick Start Guide]] | ||
− | | | + | |Homework 4<br />Lab 2 |
| | | | ||
|- | |- | ||
|12 | |12 | ||
− | |OCT | + | |OCT 4 |
− | |FPM DRAM<br />SRC FPM DRAM Design Examples | + | |FPM DRAM<br />SRC/RSRC FPM DRAM Design Examples |
− | |[[media:MT4LC8M8B6.pdf|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC FPM DRAM Design Examples]] | + | |[[media:MT4LC8M8B6.pdf|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC/RSRC FPM DRAM Design Examples]] |
− | | | + | | |
− | | | + | | |
|- | |- | ||
|13 | |13 | ||
− | |OCT | + | |OCT 9 |
|SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM | |SDRAM<br />DDR DRAM<br />DDR2 DRAM<br />DDR3 DRAM | ||
|[[media:DRAM_TYPES.pdf|DRAM Types]]<br />[[media:MT48LCM8A2.pdf|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs] | |[[media:DRAM_TYPES.pdf|DRAM Types]]<br />[[media:MT48LCM8A2.pdf|MT48LC8M8A2 SDRAM Datasheet]]<br />[[media:1GbDDRx4x8x16.pdf|MT46V128M8 DDR DRAM Datasheet]]<br />[[media:2gbddr2.pdf|MT47H256M8 DDR2 DRAM Datasheet]]<br />[[media:4Gb_DDR3_SDRAM.pdf|MT41J512M8 DDR3 DRAM Datasheet]]<br />[[media:8Gb_DDR4_SDRAM.pdf|MT40A1G8 DDR4 DRAM]]<br />[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start DDR2 Core for Digilent NEXYS4DDR Board]<br />[https://www.xilinx.com/products/intellectual-property/ddr3.html Xilinx DDR3 Core for 7 Series FPGAs] | ||
| | | | ||
− | | | + | |Homework 4 |
|- | |- | ||
|14 | |14 | ||
− | |OCT | + | |OCT 11 |
|Cache<br />Virtual Memory | |Cache<br />Virtual Memory | ||
− | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] | + | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC/RSRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC/RSRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] |
|Homework 5 | |Homework 5 | ||
− | | | + | | |
|- | |- | ||
| | | | ||
− | |OCT | + | |OCT 16 |
|Fall Break | |Fall Break | ||
| | | | ||
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|- | |- | ||
|15 | |15 | ||
− | |OCT | + | |OCT 18 |
|Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | |Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | ||
|[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | |[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | ||
− | | | + | |Lab 3 |
− | | | + | |Lab 2 |
|- | |- | ||
|16 | |16 | ||
− | |OCT | + | |OCT 23 |
|The PCI Bus | |The PCI Bus | ||
|[[media:PCI_Lecture.pdf|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]] | |[[media:PCI_Lecture.pdf|PCI Lecture Notes]]<br />[[media:X86_Chipset_Evolution.pdf|X86 Chipset Evolution]] | ||
| | | | ||
− | | | + | |Homework 5 |
|- | |- | ||
|17 | |17 | ||
− | |OCT | + | |OCT 25 |
|Serial vs. Parallel I/O Buses<br />PCIe | |Serial vs. Parallel I/O Buses<br />PCIe | ||
|[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | |[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | ||
− | |Homework | + | |Homework 6 |
− | | | + | | |
|- | |- | ||
|18 | |18 | ||
− | |OCT | + | |OCT 30 |
|Parity<br />Hamming Codes<br />ECC Memory | |Parity<br />Hamming Codes<br />ECC Memory | ||
|[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Coding_Theory_001.pdf|Coding Theory 101]]<br />[[media:Hamming_Code_Example_With_Odd_Parity.pdf|Hamming Codes]]<br />[http://www.verien.com/pcie_primer.htm PCIe CRC] | |[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Coding_Theory_001.pdf|Coding Theory 101]]<br />[[media:Hamming_Code_Example_With_Odd_Parity.pdf|Hamming Codes]]<br />[http://www.verien.com/pcie_primer.htm PCIe CRC] | ||
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|- | |- | ||
|19 | |19 | ||
− | |NOV | + | |NOV 1 |
|Disks<br />Video<br />DACs<br />ADCs | |Disks<br />Video<br />DACs<br />ADCs | ||
|[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | |[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | ||
− | |||
| | | | ||
+ | |Homework 6 | ||
|- | |- | ||
|20 | |20 | ||
− | |NOV | + | |NOV 6 |
|USB 2.0/3.0<br />IEEE 1394 (Firewire) | |USB 2.0/3.0<br />IEEE 1394 (Firewire) | ||
|[[media:Ch10CSDA.pdf|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]] | |[[media:Ch10CSDA.pdf|Chapter 10]]<br />[[media:Usb_20.pdf|USB 2.0 Specification]] | ||
| | | | ||
+ | |Lab 3 | ||
|- | |- | ||
|21 | |21 | ||
− | |NOV | + | |NOV 8 |
|Exam 2 | |Exam 2 | ||
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|- | |- | ||
|22 | |22 | ||
− | |NOV | + | |NOV 13 |
− | | | + | |Very Long Instruction Word (VLIW) Computing<br />Superscalar/Out-of-Order Processing |
− | |[[media: | + | |[[media:CPU History.pdf|CPU History]]<br />[[media:Fisher_Paper_1.pdf|Fisher Paper 1]]<br />[[media:Fisher_Paper_2.pdf|Fisher Paper 2]]<br />[[media:VLIW.pdf|VLIW Notes]]<br />[[media:K7pres.pdf|AMD K7 Presentation]] |
− | | | + | | |
| | | | ||
|- | |- | ||
|23 | |23 | ||
− | |NOV | + | |NOV 15 |
− | + | |Explicitly Parallel Instruction Computing (EPIC)<br />64-Bit Desktop Computing: AMD vs. Intel | |
− | | | + | |[[media:Itanium.ua_ovw.pdf|Intel Intanium]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]] |
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|- | |- | ||
|24 | |24 | ||
− | |NOV | + | |NOV 20 |
− | | | + | |Transmeta Crusoe |
− | |[ | + | |[https://www.ece.iastate.edu/profiles/david-ditzel David Ditzel]<br />[[media:Paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper]]<br />[[media:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop]] |
− | | | + | | |
− | | | + | | |
|- | |- | ||
| | | | ||
− | |NOV | + | |NOV 22 |
|Thanksgiving Break | |Thanksgiving Break | ||
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|- | |- | ||
|25 | |25 | ||
− | |NOV | + | |NOV 27 |
− | | | + | |Symmetric Multiprocessing (SMP)<br />Simultaneous Multithreading (SMT)<br />Introduction to Multicore/Cache Coherency<br />→Global Directory<br />→MESI (Snoopy/Pentium II)<br />→MOESI (ccNUMA/AMD Hammer)<br />→MESIF (ccNUMA/Intel Xeon Phi) |
− | |[[media: | + | |[[media:Intel-core-x-series-processor-overview.pdf|Intel Core i9]]<br />[[media:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5]]<br />[[media:01675013.pdf|Censier Paper]]<br />[[media:Papamarcos.isca84.pdf|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]<br />[[media:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi]] |
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|- | |- | ||
|26 | |26 | ||
− | |NOV | + | |NOV 29 |
− | | | + | |Deep Dive: The Illinois Protocol (MESI) |
− | | | + | |[[media:Papamarcos.isca84.pdf|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]] |
− | | | + | | |
| | | | ||
|- | |- | ||
|27 | |27 | ||
− | |DEC | + | |DEC 4 |
|Supercomputing | |Supercomputing | ||
− | | | + | |[https://en.wikipedia.org/wiki/TOP500 Top 500]<br />[https://en.wikipedia.org/wiki/FLOPS FLOPS]<br />[http://www.roylongbottom.org.uk/linpack%20results.htm Longbottom's Linpack Page]<br /n>[https://www.mir.wustl.edu/research/research-support-facilities/center-for-high-performance-computing-chpc WUSTL CHPC]<br />[https://source.wustl.edu/2017/12/view-12-4-17/#jp-carousel-245238 CHPC Photo]<br />[http://clusters.engineering.wustl.edu/index.php/Lab_Cluster WUSTL SEAS Linux Lab Cluster] |
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|- | |- | ||
|28 | |28 | ||
− | |DEC | + | |DEC 6 |
− | + | |Exam 3 | |
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