Difference between revisions of "Syllabus"
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|RISC vs. CISC<br />The Really Simple RISC (RSRC)<br />SRC Assembly Language | |RISC vs. CISC<br />The Really Simple RISC (RSRC)<br />SRC Assembly Language | ||
|[[media:Ch2CSDA.pdf|Chapter 2]]<br />[[media:RISC.pdf|The Case for the RISC]]<br />[https://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) David Patterson]<br />[https://www.ece.iastate.edu/profiles/david-ditzel/ David Ditzel]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer]] | |[[media:Ch2CSDA.pdf|Chapter 2]]<br />[[media:RISC.pdf|The Case for the RISC]]<br />[https://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) David Patterson]<br />[https://www.ece.iastate.edu/profiles/david-ditzel/ David Ditzel]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer]] | ||
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|1-Bus SRC Microarchitecture<br />1-Bus SRC Concrete RTN | |1-Bus SRC Microarchitecture<br />1-Bus SRC Concrete RTN | ||
|[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:1-Bus_Block_Diagrams.pdf|1-Bus SRC Block Diagrams]]<br />[[media:1busrtn.pdf |1-Bus SRC RTN]] | |[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:1-Bus_Block_Diagrams.pdf|1-Bus SRC Block Diagrams]]<br />[[media:1busrtn.pdf |1-Bus SRC RTN]] | ||
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|Microprogramming the SRC | |Microprogramming the SRC | ||
|[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Microprogrammed_SRC_Control_Unit.pdf|Microprogrammed SRC Control Unit]]<br />[[media:Control.pdf|Microprogrammed SRC CONTROL.VHD]]<br />[[media:Controlstore.pdf|Microprogrammed SRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded SRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]] | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Microprogrammed_SRC_Control_Unit.pdf|Microprogrammed SRC Control Unit]]<br />[[media:Control.pdf|Microprogrammed SRC CONTROL.VHD]]<br />[[media:Controlstore.pdf|Microprogrammed SRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded SRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]] | ||
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|1-Bus vs 2-Bus vs 3-Bus Microarchitecture<br />Introduction to Pipelining | |1-Bus vs 2-Bus vs 3-Bus Microarchitecture<br />Introduction to Pipelining | ||
|[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf|3-Bus SRC Block Diagrams]]<br />[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC]] | |[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:Two_Bus_SRC.pdf|2-Bus SRC Block Diagrams]]<br />[[media:3_Bus_Block_Diagrams.pdf|3-Bus SRC Block Diagrams]]<br />[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC]] | ||
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|Review | |Review | ||
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|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Am27c256.pdf|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:Cy7c199n_8.pdf|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf|SRAM Example]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Am27c256.pdf|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:Cy7c199n_8.pdf|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf|SRAM Example]] | ||
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|FPM DRAM<br />SRC FPM DRAM Design Examples | |FPM DRAM<br />SRC FPM DRAM Design Examples | ||
|[[media:MT4LC8M8B6.pdf|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC FPM DRAM Design Examples]] | |[[media:MT4LC8M8B6.pdf|FPM DRAM Datasheet]]<br />[[media:FPM_DRAM_Example.pdf|SRC FPM DRAM Design Examples]] | ||
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|Cache<br />Virtual Memory | |Cache<br />Virtual Memory | ||
|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Cache_Example.pdf|SRC Cache Example]]<br />[[media:SRC_Cache_Datapath.pdf|SRC Cache Datapath Example]]<br />[[media:Intel_Haswell_Cache.png|Intel Core i7 (Haswell) Cache Parameters]]<br />[[media:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts]]<br />[[media:Virtual_Memory_H&P.pdf|Virtual Memory H&P]] | ||
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|Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | |Memory-Mapped I/O<br />Shared I/O<br />Polling<br />Interrupt-Driven I/O<br />Direct Memory Access (DMA)<br />The Multi-Master SRC Bus<br />Bus Arbitration | ||
|[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | |[[media:Ch8CSDA.pdf|Chapter 8]]<br />[[media:Stereo.pdf|SRC Stereo Card Bus Alternatives]]<br />[[media:IN_OUT_RTN.pdf|SRC IN and OUT RTN]]<br />[[media:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|Three-Slot Multi-Master SRC Motherboard]] | ||
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|Serial vs. Parallel I/O Buses<br />PCIe | |Serial vs. Parallel I/O Buses<br />PCIe | ||
|[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | |[[media:LTSPICE_TUTORIAL.pdf|LTSPICE Tutorial]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[[media:PCIe_Lecture.pdf|PCIe Lecture]] | ||
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|Disks<br />Video<br />DACs<br />ADCs | |Disks<br />Video<br />DACs<br />ADCs | ||
|[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | |[[media:Ch9CSDA.pdf|Chapter 9]]<br />[[media:Video_Example.pdf|SRC Video Example]]<br />[[media:R2R_DAC.pdf|R2R DAC Example]]<br />[[media:2-Bit_Flash_ADC.pdf|Flash ADC Example]] | ||
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|Introduction to Pipelining | |Introduction to Pipelining | ||
|[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:RISC.pdf|The Case for RISC]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC]] | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:RISC.pdf|The Case for RISC]]<br />[[media:BasicPipelinedSRC.pdf|Basic Pipelined SRC]] | ||
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|Microprogramming the SRC | |Microprogramming the SRC | ||
|[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Microprogrammed_SRC_Control_Unit.pdf|Microprogrammed SRC Control Unit]]<br />[[media:Control.pdf|Microprogrammed SRC CONTROL.VHD]]<br />[[media:Controlstore.pdf|Microprogrammed SRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded SRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]] | |[[media:Ch5CSDA.pdf|Chapter 5]]<br />[[media:Microprogrammed_SRC_Control_Unit.pdf|Microprogrammed SRC Control Unit]]<br />[[media:Control.pdf|Microprogrammed SRC CONTROL.VHD]]<br />[[media:Controlstore.pdf|Microprogrammed SRC CONTROLSTORE.VHD]]<br />[[media:Microcodedsrcvhdl.zip|Microcoded SRC VHDL Zip File]]<br />[[media:64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf|Intel Software Developer's Manual (see pages 285, 339)]] | ||
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|Transmeta Crusoe<br />Symmetric Multiprocessing (SMP)<br />Simultaneous Multithreading (SMT)<br />Introduction to Multicore/Cache Coherency<br />→Global Directory<br />→MESI (Snoopy/Pentium II)<br />→MOESI (ccNUMA/AMD Hammer)<br />→MESIF (ccNUMA/Intel Xeon Phi) | |Transmeta Crusoe<br />Symmetric Multiprocessing (SMP)<br />Simultaneous Multithreading (SMT)<br />Introduction to Multicore/Cache Coherency<br />→Global Directory<br />→MESI (Snoopy/Pentium II)<br />→MOESI (ccNUMA/AMD Hammer)<br />→MESIF (ccNUMA/Intel Xeon Phi) | ||
|[https://www.ece.iastate.edu/profiles/david-ditzel David Ditzel]<br />[[media:Paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper]]<br />[[media:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop]]<br />[[media:Intel-core-x-series-processor-overview.pdf|Intel Core i9]]<br />[[media:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5]]<br />[[media:01675013.pdf|Censier Paper]]<br />[[media:Papamarcos.isca84.pdf|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]<br />[[media:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi]] | |[https://www.ece.iastate.edu/profiles/david-ditzel David Ditzel]<br />[[media:Paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper]]<br />[[media:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop]]<br />[[media:Intel-core-x-series-processor-overview.pdf|Intel Core i9]]<br />[[media:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5]]<br />[[media:01675013.pdf|Censier Paper]]<br />[[media:Papamarcos.isca84.pdf|Illinois Protocol Paper (1984)]]<br />[[media:29056402.pdf|Intel Pentium II MESI Chipset]]<br />[[media:MPF_Hammer_Presentation.pdf|AMD Hammer]]<br />[[media:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi]] | ||
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