Difference between revisions of "Syllabus"
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|SEPT 28 | |SEPT 28 | ||
|Introduction to Memory<br />Memory Space Decoding<br />Introduction to Schematic Capture | |Introduction to Memory<br />Memory Space Decoding<br />Introduction to Schematic Capture | ||
− | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Am27c256.pdf|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:SRAM_Example.pdf|SRAM Example]] | + | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:Am27c256.pdf|AM27C256 EPROM Datasheet]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:Cy7c199n_8.pdf|CY7C199N SRAM Datasheet]]<br />[[media:SRAM_Example.pdf|SRAM Example]] |
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|Homework 4 | |Homework 4 |
Revision as of 16:51, 17 May 2017
LECTURE | DATE | TOPICS | PREPARATION | DUE | ASSIGNED |
1 | AUG 29 | Course Introduction Classification of Computers and Instructions RISC vs. CISC |
Course Introduction Chapter 1 Chapter 2 |
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2 | AUG 31 | Addressing Modes The Simple RISC Computer (Introduction) SRC Assembly Language |
Chapter 2 | Homework 1 | |
3 | SEPT 5 | SRC Abstract RTN Displacement-Based Addressing |
Chapter 2 SRC Abstract RTN Displacement-Based Addressing |
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4 | SEPT 7 | 1-Bus SRC Microarchitecture 1-Bus SRC Concrete RTN |
Chapter 4 1-Bus SRC Block Diagrams |
Homework 1 | Homework 2 |
5 | SEPT 12 | 1-Bus SRC Control FSM 2-Bus SRC Microarchitecture 3-Bus SRC Microarchitecture |
Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams |
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6 | SEPT 14 | SRC VHDL Implementation | 1-Bus SRC VHDL | Homework 2 | Homework 3 |
7 | SEPT 19 | SRC FPGA Implementation | 1-BUS SRC Xilinx ISE 14.7 Tutorial |
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8 | SEPT 21 | Interrupts/Exceptions | Chapter 4 | Homework 3 | |
9 | SEPT 26 | Exam 1 | |||
10 | SEPT 28 | Introduction to Memory Memory Space Decoding Introduction to Schematic Capture |
Chapter 7 AM27C256 EPROM Datasheet EPROM Example CY7C199N SRAM Datasheet SRAM Example |
Homework 4 | |
11 | OCT 3 | Schematic Capture Details Memory Boards and Modules |
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12 | OCT 5 | FPM DRAM SRC FPM DRAM Design Examples |
FPM DRAM Datasheet SRC FPM DRAM Design Examples |
Homework 4 | Homework 5 |
13 | OCT 10 | SDRAM DDR DRAM DDR2 DRAM DDR3 DRAM |
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14 | OCT 12 | Cache Virtual Memory |
Chapter 7 SRC Cache Example Virtual Memory Concepts |
Homework 5 | Homework 6 |
OCT 17 | Fall Break | ||||
15 | OCT 19 | Memory-Mapped I/O Shared I/O Polling Interrupt-Driven I/O Direct Memory Access (DMA) The Multi-Master SRC Bus Bus Arbitration |
Chapter 8 SRC Stereo Card Bus Alternatives Three-Slot Multi-Master SRC Motherboard |
Homework 6 | Homework 7 |
16 | OCT 24 | PCI Bus | PCI Lecture Notes | ||
17 | OCT 26 | Serial vs. Parallel I/O Buses PCIe |
Reflection Lecture PCIe Lecture |
Homework 7 | Homework 8 |
18 | OCT 31 | Parity Hamming Codes ECC Memory |
Chapter 8 Coding Theory 101 |
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19 | NOV 2 | Disks Video DACs ADCs |
Chapter 9 SRC Video Example R2R DAC Example Flash ADC Example |
Homework 8 | |
20 | NOV 7 | USB 2.0/3.0 IEEE 1394 (Firewire) |
Chapter 10 | ||
21 | NOV 9 | Exam 2 | |||
22 | NOV 14 | Introduction to Pipelining | Chapter 5 | Homework 9 | |
23 | NOV 16 | Pipelining the SRC | Chapter 5 | ||
24 | NOV 21 | Microprogramming the SRC | Chapter 5 | Homework 9 | Homework 10 |
NOV 23 | Thanksgiving Break | ||||
25 | NOV 28 | VLIW Superscalar Transmeta Crusoe |
Chapter 5 Transmeta Crusoe White Paper |
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26 | NOV 30 | Introduction to Multicore/Cache Coherency | Homework 10 | ||
27 | DEC 5 | Supercomputing | |||
28 | DEC 7 | Exam 3 |