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Date Name Thumbnail Size User Description Versions
20:12, 18 February 2014 StateEqualOutputTechnology2.pdf (file) 12 KB Wdr   1
20:31, 10 February 2014 Stateequaloutputsynthesisreport.txt (file) 15 KB Wdr   1
20:27, 10 February 2014 StateEqualOutputTechnology.pdf (file) 12 KB Wdr   1
20:24, 10 February 2014 Stateequaloutput.vhd (file) 2 KB Wdr   1
16:46, 4 February 2014 Ieeetc86.pdf (file) 95 KB Wdr   1
16:03, 3 February 2014 Tcad-feb-2007.pdf (file) 886 KB Wdr   1
16:01, 3 February 2014 A tutorial on logic synthesis for lookup-table based FPGAs.pdf (file) 774 KB Wdr   1
20:49, 31 January 2014 BDDs.pdf (file) 97 KB Wdr   1
21:15, 28 January 2014 Boole’s Expansion Theorem.pdf (file) 482 KB Wdr   1
21:02, 24 January 2014 Technology Mapping.pdf (file) 66 KB Wdr   1
19:14, 23 January 2014 Arctanbit0output.txt (file) 8 KB Wdr   1
19:06, 23 January 2014 Arctanbit0.txt (file) 64 KB Wdr   1
21:07, 22 January 2014 ITERATED CONSENSUS.pdf (file) 89 KB Wdr   1
21:15, 21 January 2014 Decomposition By Expansion.pdf (file) 277 KB Wdr   1
17:51, 21 January 2014 MULTIPLE OUTPUT FUNCTIONS.pdf (file) 95 KB Wdr   1
15:44, 21 January 2014 Don't Cares.pdf (file) 55 KB Wdr   1
15:35, 21 January 2014 Reduction Techniques.pdf (file) 111 KB Wdr   1
21:55, 16 January 2014 SYNTHESIS OF TWO-LEVEL CIRCUITS.pdf (file) 71 KB Wdr   1
21:55, 16 January 2014 K Maps.pdf (file) 90 KB Wdr   1
21:54, 16 January 2014 Quine-McCluskey.pdf (file) 60 KB Wdr   1
16:35, 13 January 2014 Xor.txt (file) 90 bytes Wdr   1
17:27, 19 April 2012 Cypress 2KX9 FIFO.pdf (file) 644 KB Wdr   1
15:44, 17 April 2012 Kohavi.pdf (file) 1.28 MB Wdr   1
17:27, 6 April 2012 Clockgate.pdf (file) 9 KB Wdr   1
17:26, 6 April 2012 CLOCKGATE.vhd (file) 601 bytes Wdr   1
17:59, 3 April 2012 Clocked NOR Latch.jpg (file) 12 KB Wdr   1
17:42, 3 April 2012 Dflopsim2.pdf (file) 9 KB Wdr   1
17:42, 3 April 2012 Dflopsim.pdf (file) 9 KB Wdr   1
17:33, 3 April 2012 NOR Latch.jpg (file) 18 KB Wdr   1
17:28, 3 April 2012 Norlatchsim.pdf (file) 8 KB Wdr   1
17:27, 3 April 2012 NOR LATCH.vhd (file) 464 bytes Wdr   1
17:02, 3 April 2012 Edge-Triggered D Flip-Flop.jpg (file) 28 KB Wdr   1
16:54, 3 April 2012 D FLIP FLOP.vhd (file) 791 bytes Wdr   1
16:05, 28 February 2012 Simplification by Implication Tables.pdf (file) 53 KB Wdr   1
20:24, 23 February 2012 Figure7dot4WithFiveStates.vhd (file) 2 KB Wdr   1
15:29, 23 February 2012 Xst v6s6.pdf (file) 2.49 MB Wdr   1
16:18, 16 February 2012 Figure7dot4v4.pdf (file) 9 KB Wdr   1
16:15, 16 February 2012 Figure7dot4v4.vhd (file) 1 KB Wdr   1
16:14, 16 February 2012 DefaultV4SynthesisReport.txt (file) 16 KB Wdr   1
19:24, 13 February 2012 DefaultV3SynthesisReport.txt (file) 15 KB Wdr   1
19:24, 13 February 2012 DefaultV2SynthesisReport.txt (file) 16 KB Wdr   1
19:12, 13 February 2012 DefaultV1SynthesisReport.txt (file) 16 KB Wdr   1
19:10, 13 February 2012 Figure7dot4v3.vhd (file) 2 KB Wdr   1
19:04, 13 February 2012 Figure7dot4v2.vhd (file) 2 KB Wdr   1
18:20, 13 February 2012 Example12Technology.pdf (file) 10 KB Wdr   1
18:19, 13 February 2012 Figure7dot4.pdf (file) 10 KB Wdr   1
18:15, 13 February 2012 Figure7dot4.vhd (file) 2 KB Wdr   1
16:33, 9 February 2012 Bit Zero Optimal LUTs.pdf (file) 33 KB Wdr   1
18:49, 5 February 2012 Example9TechnologyPH.bmp (file) 1.44 MB Wdr   1
18:08, 5 February 2012 Example11Technology.pdf (file) 28 KB Wdr   1
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