CSE365

Elements of Computing Systems

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Assignment 3

Due Date: 2015-2-8, 11:59pm

Objective

Complete HDL implementations for the following 8 gates so that the tests are successful.

1. Bit
2. Register
3. PC
4. RAM8
5. RAM64
6. RAM512
7. RAM4K
8. RAM16K

Tips and Resources

• This is another copy/paste heavy assignment, but it should be the last.
• You may use any gates from Assignments 1 and 2, as well as the DFF (Data Flip Flop gate).
• The files for this assignment are in two separate folders to force the simulator to not use your implementations of the chips in the first half for the chips in the second half. Otherwise it would need to simulate thousands upon thousands of DFFs for the higher level chips.
• Chapter 3