Difference between revisions of "Syllabus"
From CSE362 Wiki
Jump to navigationJump to searchLine 219: | Line 219: | ||
|25 | |25 | ||
|NOV 28 | |NOV 28 | ||
− | |VLIW | + | |VLIW<br />Superscalar<br />Transmeta Crusoe |
|[[media:Ch5CSDA.pdf|Chapter 5]] | |[[media:Ch5CSDA.pdf|Chapter 5]] | ||
| | | |
Revision as of 14:53, 17 May 2017
LECTURE | DATE | TOPICS | PREPARATION | DUE | ASSIGNED |
1 | AUG 29 | Course Introduction Classification of Computers and Instructions RISC vs. CISC |
Course Introduction Chapter 1 Chapter 2 |
||
2 | AUG 31 | Addressing Modes The Simple RISC Computer (Introduction) SRC Assembly Language |
Chapter 2 | Homework 1 | |
3 | SEPT 5 | SRC Abstract RTN Displacement-Based Addressing |
Chapter 2 SRC Abstract RTN Displacement-Based Addressing |
||
4 | SEPT 7 | 1-Bus SRC Microarchitecture 1-Bus SRC Concrete RTN |
Chapter 4 1-Bus SRC Block Diagrams |
Homework 1 | Homework 2 |
5 | SEPT 12 | 1-Bus SRC Control FSM 2-Bus SRC Microarchitecture 3-Bus SRC Microarchitecture |
Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams |
||
6 | SEPT 14 | SRC VHDL Implementation | 1-Bus SRC VHDL | Homework 2 | Homework 3 |
7 | SEPT 19 | SRC FPGA Implementation | 1-BUS SRC Xilinx ISE 14.7 Tutorial |
||
8 | SEPT 21 | Interrupts/Exceptions | Chapter 4 | Homework 3 | |
9 | SEPT 26 | Exam 1 | |||
10 | SEPT 28 | Introduction to Memory Memory Space Decoding Schematic Capture Concepts |
Chapter 7 EPROM Example SRAM Example |
Homework 4 | |
11 | OCT 3 | ||||
12 | OCT 5 | Homework 4 | Homework 5 | ||
13 | OCT 10 | ||||
14 | OCT 12 | Cache Virtual Memory |
Chapter 7 SRC Cache Example Virtual Memory Concepts |
Homework 5 | Homework 6 |
OCT 17 | Fall Break | ||||
15 | OCT 19 | Memory-Mapped I/O Shared I/O Polling Interrupt-Driven I/O Direct Memory Access Multimaster SRC Bus |
Chapter 8 SRC Stereo Card Bus Alternatives |
Homework 6 | Homework 7 |
16 | OCT 24 | PCI Bus | |||
17 | OCT 26 | Serial vs. Parallel I/O Buses PCIe |
Homework 7 | Homework 8 | |
18 | OCT 31 | Parity Hamming Codes ECC Memory |
|||
19 | NOV 2 | Disks Video |
Homework 8 | ||
20 | NOV 7 | USB 2.0/3.0 IEEE 1394 (Firewire) |
|||
21 | NOV 9 | Exam 2 | |||
22 | NOV 14 | Introduction to Pipelining | Chapter 5 | Homework 9 | |
23 | NOV 16 | Pipelining the SRC | Chapter 5 | ||
24 | NOV 21 | Microprogramming the SRC | Chapter 5 | Homework 9 | Homework 10 |
NOV 23 | Thanksgiving Break | ||||
25 | NOV 28 | VLIW Superscalar Transmeta Crusoe |
Chapter 5 | ||
26 | NOV 30 | Introduction to Multicore/Cache Coherency | Homework 10 | ||
27 | DEC 5 | Supercomputing | |||
28 | DEC 7 | Exam 3 |