Difference between revisions of "Lecture Notes"
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*[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] | *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] | ||
*[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] | *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] | ||
| + | *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] | ||
| + | *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] | ||
*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
Revision as of 21:24, 2 February 2012
- Standard Cell Example
- Espresso Example
- Espresso Example Output
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 2
- VHDL Example 2 Synthesized RTL Schematic
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 3
- VHDL Example 4
- VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 5
- VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 6
- VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 7
- VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 8
- VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic
- Altera vs. Xilinx
- Xilinx vs. Altera
- Altera Logic Efficiency Analysis
- Altera FPGA Architecture White Paper
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
