Syllabus

FALL 2017 (UNDER CONSTRUCTION)

LECTURE	DATE	TOPICS	PREPARATION	ASSIGNED	DUE
1	AUG 29	Course Introduction Classification of Computers and Instructions RISC vs. CISC	Course Introduction Chapter 1 Chapter 2
2	AUG 31	Addressing Modes The Simple RISC Computer (Introduction) SRC Assembly Language	Chapter 2	Homework 1
3	SEPT 5	SRC Abstract RTN Displacement-Based Addressing	Chapter 2 SRC Abstract RTN Displacement-Based Addressing
4	SEPT 7	1-Bus SRC Microarchitecture Datapath Refinement 1-Bus SRC Concrete RTN	Chapter 4 1-Bus SRC Block Diagrams	Homework 2	Homework 1
5	SEPT 12	1-Bus SRC Control FSM 2-Bus SRC Microarchitecture 3-Bus SRC Microarchitecture	Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams
6	SEPT 14	SRC VHDL Implementation	1-Bus SRC VHDL	Homework 3	Homework 2
7	SEPT 19	SRC FPGA Implementation	1-BUS SRC Xilinx ISE 14.7 Tutorial
8	SEPT 21	Interrupts/Exceptions	Chapter 4		Homework 3
9	SEPT 26	Review
10	SEPT 28	Exam 1
11	OCT 3	Introduction to Memory Memory Space Decoding	Chapter 7 EPROM Example SRAM Example	Homework 4
12	OCT 5			Homework 5	Homework 4
13	OCT 10
14	OCT 12			Homework 6	Homework 5
15	OCT 19
16	OCT 24			Homework 7	Homework 6
17	OCT 26
18	OCT 31			Homework 8	Homework 7
19	NOV 2
20	NOV 7			Homework 8
21	NOV 9
22	NOV 14	Exam 2
23	NOV 16	Introduction to Pipelining	Chapter 5	Homework 9
24	NOV 21	Pipelining the SRC	Chapter 5
25	NOV 28	Microprogramming the SRC	Chapter 5	Homework 10	Homework 9
26	NOV 30	VLIW, Superscalar	Chapter 5
27	DEC 5	Introduction to Multicore/Cache Coherency			Homework 10
28	DEC 7	Exam 3