Difference between revisions of "Syllabus"
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|TOPICS | |TOPICS | ||
|PREPARATION | |PREPARATION | ||
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|Addressing Modes<br />The Simple RISC Computer (Introduction)<br />SRC Assembly Language | |Addressing Modes<br />The Simple RISC Computer (Introduction)<br />SRC Assembly Language | ||
|[[media:Ch2CSDA.pdf|Chapter 2]] | |[[media:Ch2CSDA.pdf|Chapter 2]] | ||
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|Homework 1 | |Homework 1 | ||
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|1-Bus SRC Microarchitecture<br />Datapath Refinement<br />1-Bus SRC Concrete RTN | |1-Bus SRC Microarchitecture<br />Datapath Refinement<br />1-Bus SRC Concrete RTN | ||
|[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:1-Bus_Block_Diagrams.pdf|1-Bus SRC Block Diagrams]] | |[[media:Ch4WDR.pdf|Chapter 4]]<br />[[media:1-Bus_Block_Diagrams.pdf|1-Bus SRC Block Diagrams]] | ||
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|SRC VHDL Implementation | |SRC VHDL Implementation | ||
|[[media:Srcvhdl.zip|1-Bus SRC VHDL]] | |[[media:Srcvhdl.zip|1-Bus SRC VHDL]] | ||
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|Homework 3 | |Homework 3 | ||
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|Interrupts/Exceptions | |Interrupts/Exceptions | ||
|[[media:Ch4WDR.pdf|Chapter 4]] | |[[media:Ch4WDR.pdf|Chapter 4]] | ||
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|Introduction to Memory<br />Memory Space Decoding<br />Schematic Capture Concepts | |Introduction to Memory<br />Memory Space Decoding<br />Schematic Capture Concepts | ||
|[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:SRAM_Example.pdf|SRAM Example]] | |[[media:Ch7CSDA.pdf|Chapter 7]]<br />[[media:EPROM_Example.pdf|EPROM Example]]<br />[[media:SRAM_Example.pdf|SRAM Example]] | ||
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|[[media:Ch5CSDA.pdf|Chapter 5]] | |[[media:Ch5CSDA.pdf|Chapter 5]] | ||
|Homework 9 | |Homework 9 | ||
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|Microprogramming the SRC | |Microprogramming the SRC | ||
|[[media:Ch5CSDA.pdf|Chapter 5]] | |[[media:Ch5CSDA.pdf|Chapter 5]] | ||
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|Homework 10 | |Homework 10 | ||
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|Introduction to Multicore/Cache Coherency | |Introduction to Multicore/Cache Coherency | ||
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Revision as of 14:06, 17 May 2017
| LECTURE | DATE | TOPICS | PREPARATION | DUE | ASSIGNED |
| 1 | AUG 29 | Course Introduction Classification of Computers and Instructions RISC vs. CISC |
Course Introduction Chapter 1 Chapter 2 |
||
| 2 | AUG 31 | Addressing Modes The Simple RISC Computer (Introduction) SRC Assembly Language |
Chapter 2 | Homework 1 | |
| 3 | SEPT 5 | SRC Abstract RTN Displacement-Based Addressing |
Chapter 2 SRC Abstract RTN Displacement-Based Addressing |
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| 4 | SEPT 7 | 1-Bus SRC Microarchitecture Datapath Refinement 1-Bus SRC Concrete RTN |
Chapter 4 1-Bus SRC Block Diagrams |
Homework 1 | Homework 2 |
| 5 | SEPT 12 | 1-Bus SRC Control FSM 2-Bus SRC Microarchitecture 3-Bus SRC Microarchitecture |
Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams |
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| 6 | SEPT 14 | SRC VHDL Implementation | 1-Bus SRC VHDL | Homework 2 | Homework 3 |
| 7 | SEPT 19 | SRC FPGA Implementation | 1-BUS SRC Xilinx ISE 14.7 Tutorial |
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| 8 | SEPT 21 | Interrupts/Exceptions | Chapter 4 | Homework 3 | |
| 9 | SEPT 26 | Exam 1 | |||
| 10 | SEPT 28 | Introduction to Memory Memory Space Decoding Schematic Capture Concepts |
Chapter 7 EPROM Example SRAM Example |
Homework 4 | |
| 11 | OCT 3 | ||||
| 12 | OCT 5 | Homework 4 | Homework 5 | ||
| 13 | OCT 10 | ||||
| 14 | OCT 12 | Homework 5 | Homework 6 | ||
| 15 | OCT 17 | Fall Break | |||
| 15 | OCT 19 | Homework 6 | Homework 7 | ||
| 16 | OCT 24 | ||||
| 17 | OCT 26 | Homework 7 | Homework 8 | ||
| 18 | OCT 31 | ||||
| 19 | NOV 2 | Homework 8 | |||
| 20 | NOV 7 | ||||
| 21 | NOV 9 | Exam 2 | |||
| 22 | NOV 14 | Introduction to Pipelining | Chapter 5 | Homework 9 | |
| 23 | NOV 16 | Pipelining the SRC | Chapter 5 | ||
| 24 | NOV 21 | Microprogramming the SRC | Chapter 5 | Homework 9 | Homework 10 |
| 24 | NOV 23 | Thanksgiving Break | |||
| 25 | NOV 28 | VLIW, Superscalar | Chapter 5 | ||
| 26 | NOV 30 | Introduction to Multicore/Cache Coherency | Homework 10 | ||
| 27 | DEC 5 | Supercomputing | |||
| 28 | DEC 7 | Exam 3 |
