Difference between revisions of "Syllabus"

Revision as of 18:49, 10 May 2017

FALL 2017
LECTURE	DATE	TOPICS	PREPARATION	ASSIGNED	DUE
1	AUG 29	Course Introduction Classification of Computers and Instructions RISC vs. CISC	Course Introduction Chapter 1 Chapter 2
2	AUG 31	Addressing Modes The Simple RISC Computer (Introduction) SRC Assembly Language	Chapter 2	Homework 1
3	SEPT 5	SRC Abstract RTN Displacement-Based Addressing	Chapter 2 SRC Abstract RTN Displacement-Based Addressing
4	SEPT 7	1-Bus SRC Microarchitecture Datapath Refinement 1-Bus SRC Concrete RTN	Chapter 4 1-Bus SRC Block Diagrams	Homework 2	Homework 1
5	SEPT 12	1-Bus SRC Control FSM 2-Bus SRC Microarchitecture 3-Bus SRC Microarchitecture	Chapter 4 2-Bus SRC Block Diagrams 3-Bus SRC Block Diagrams
6	SEPT 14	SRC VHDL Implementation	1-Bus SRC VHDL	Homework 3	Homework 2
7	SEPT 19	SRC FPGA Implementation	1-BUS SRC Xilinx ISE 14.7 Tutorial
8	SEPT 21				Homework 3
9	SEPT 26
10	SEPT 28	Exam 1
11	OCT 3
12	OCT 5
13	OCT 10
14	OCT 12
15	OCT 19
16	OCT 24
17	OCT 26
18	OCT 31
19	NOV 2
20	NOV 7
21	NOV 9
22	NOV 14
23	NOV 16
24	NOV 21
25	NOV 28
26	NOV 30
27	DEC 5
28	DEC 7	Exam 3

@@ Line 53: / Line 53: @@
 |SEPT 14
 |SRC VHDL Implementation
-|[[media:Srcvhdl.zip‎|1-Bus SRC VHDL]]<br />[[media:SRC_VHDL_Tutorial.pdf‎|1-BUS SRC Xilinx ISE 14.7 Tutorial]]
+|[[media:Srcvhdl.zip‎|1-Bus SRC VHDL]]
 |Homework 3
 |Homework 2
@@ Line 60: / Line 60: @@
 |7
 |SEPT 19
-|
+|SRC FPGA Implementation
-|
+|[[media:SRC_VHDL_Tutorial.pdf‎|1-BUS SRC Xilinx ISE 14.7 Tutorial]]<br />
 |
 |