Introduction to Digital Logic and Computer Design

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Updated December 11
Final exam date and time are updated.

Updated November 21
Moved lecture for Chapter 9.
Removed two classes.

Course Syllabus:

Class No. Class Date Material Covered Partial List of Topics
1 Aug 30 Chapter 1 Number systems
- Sep 04 Holiday
2 Sep 06 Chapter 2 Number systems, Codes
3 Sep 11 Chapter 4 Binary logic, Boolean algebra
4 Sep 13 Chapter 4 standard forms, K-maps
5 Sep 18 Chapter 4 K-maps
6 Sep 20 Chapter 4 multiple level optimization, NAND, NOR, XOR
7 Sep 25 Chapter 6 Combinational logic analysis
8 Sep 27 Chapter 6 Combination logic design procedure, PAL, PLA
9 Oct 02 Chapter 6 Decoder, encoder
10 Oct 04 Chapter 6 Multiplexer, addition
11 Oct 09 Chpater 6, review Addition
12 Oct 11 Test #1 Chapter 1, 2, 4, and part of 6
13 Oct 16 Chapter 6 Addition, binary numbers
14 Oct 18 Chapter 6 Multiplication
15 Oct 23 Chapter 7 Latches, flip-flops
16 Oct 25 Chapter 7 Latches, flip-flops
17 Oct 30 Chpater 7 Sequential analysis
18 Nov 01 Chapter 7 Sequential design, state diagram
19 Nov 06 Chapter 7 Sequential design, state diagram
20 Nov 08 Chapter 8 Counters, Registers
21 Nov 13 Chapter 8, review Counters, Registers
22 Nov 15 Test #2 Chapter 6 and 7
23 Nov 20 Chapter 8 Counters, Registers
- Nov 22 Holiday
24 Nov 27 Chapter 8, Chapter 9 Counters, Registers, Memory
25 Nov 29 Chapter 9, Notes Memory, RTL, ASM
26 Dec 04 Notes RTL, ASM
27 Dec 06 Notes RTL, ASM
28 Dec 11 Review
29 Dec 18 Final Exam 4:00 to 5:30