Introduction to Digital Logic and Computer Design

RTL homework:

• 1.  Show the diagram of the hardware that implements the register transfer statement:
        K --> (R1 <--R0 : R0 <-- R1)
• 2.  The outputs of registers R0, R1, R2, and R3 are connected through 4-to-1 multiplexers to the inputs of a fourth register R4.  Each register is 4 bits long.  The required transfers, as dictated by the control word (a 2-bit word) and an enable, are:
      Enable ^ (CON = 0) --> R4 <-- R0 :
      Enable ^ (CON = 1) --> R4 <-- R1 :
      Enable ^ (CON = 2) --> R4 <-- R2 :
      Enable ^ (CON = 3) --> R4 <-- R3
  Using Registers (with Load as necessary), and a multiplexer, draw a schematic of the hardware that implements a single bit of these register transfers.
  
• 3.  Using two 4-bit registers (with Load as necessary) R1 and R2, and AND gates, OR gates, and inverters, draw a schematic of a single bit of these registers that implements all of the following statements:
      K0 --> R2 <-- 1 :
      K1 --> R2 <-- R2 ^ R1' :
      K2 --> R2 <-- R1
  The control variables are mutually exclusive (i.e., only one variable can be equal to 1 at any time) while the other two are equal to 0.  Also, no transfer into R2 is to occur for all control variables equal to 0.
• 4.  A system is to have the following set of register transfers, implemented using buses:
      K0 --> R0 <-- R2 : R1 <-- R3 : R4 <-- R2
      K1 --> R0 <-- R3 : R2 <-- R4
      K2 --> R4 <-- R0 : R2 <-- R3
      K3 -->  R3 <-- R2 : R0 <-- R3
  A.  For each destination register, list all of the source registers.
  B.  For each source register, list all of the destination registers.
  C.  With consideration for which of the transfers must occur simultaneously, what is the minimum number of buses that can be used to implement the set of transfers?  Count buses that are inputs to the registers.
  D.  Draw a block diagram of the system, showing registers, multiplexers, and buses and the connections between them.  Do NOT show clock, load, or select signals.  Only show the flow of data.
  
• 5.  The following register transfers are to be executed in, at most, two clock cycles:
      R0 <-- R1
      R5 <-- R3
      R0 <-- R2
      R5 <-- R2
      R1 <-- R5
      R4 <-- R1
      R2 <-- R4
      R4 <-- R0
      R3 <-- R4
  A.  What is the minimum number of buses required?  Assume that only one bus can be attached to a register input and that any net connected to a register input is counted as a bus.
  B.  Draw a block diagrm connecting registers and multiplexers to implement the transfers.
• 6. There is an existing circuit, described below, that generates a sinusoidal waveform. The problem with the existing circuit is that it has too many circuit elements and the elements are expensive. Although the existing circuit is fast and generates a new output every clock cycle, you are to redesign this circuit to use fewer parts even though it may take several clock cycles to generate a new output.

  The circuit uses the cosine and sine addition formulas to generate the sinusoidal waveform.

  

  The delta angle is constant for a given samples per cycle. The larger the delta angle the fewer samples per cycle. Another way of writing the cosine and sine addition equations as used in the circuit is:

  

  The RTL statements for the original circuit are:

  LOAD --> (X <-- Xin : Y <-- Yin : DX <-- DXin : DY <-- DYin) :
  LOAD' --> (X <-- X * DX - Y * DY : Y <-- X * DY + Y * DX)
  

  Where the LOAD signal loads the four registers in the circuit from an external source. The block diagram (showing only the data path) for the circuit is below:

  

  Your new circuit should have the following features:

  • A. There should only be one multiplier.
  • B. There should only be one adder/subtractor.
  • C. There is only one input data bus for loading the registers.
  • D. There is only one output data bus.

  For this problem I want you to:

  • A. Write all of the RTL statements required to generate the sinusoidal waveform.
  • B. Draw a block diagram of the circuit. I am mostly interested in the data path for the circuit.
  • 1. You do not need to show the controller/sequencer circuit.
  • 2. You do not need to show a clock signal.
  • 3. You do not need to show enable, load, or mode signals.
  • C. Combine as many microoperations in one statement as possible.
  • D. Write a description of how the circuit works. Make sure you include a description of the sequence of operations for the controller.