Introduction
to Digital Logic and Computer Design
Chapter 9 homework:
- 1. A 4Mx8 DRAM memory device must have every row refreshed
within 4 mS.
The device has 4096 words per row. It takes 400 nS to refresh a row.
What
is the minimum percentage of time the DRAM is unavailable due to
refresh?
- 2. Design a 64kx16 SRAM memory circuit using 16kx4 SRAMs
and decoders.
- 3. Show the truth table for a ROM designed as a SIN(angle)
Look-Up-Table.
The angle is an 8 bit value with the least significant bit equal to
90.0/255
degrees. The output is an 8 bit value with the least significant bit
equal
to 1.0/128.0. Only show the truth table for addresses 120 to 140. Do
not
show the fuse map.
- 4. A memory circuit is to be designed to hold a video image
that has
been sampled at 8 bits per picture element (pixel). The image size is
640x480 pixels. How many 64Kx1 SRAMs will it take to hold the video
image?