Introduction to Digital Logic and Computer Design

Chapter 8 homework:

• 1. Design a variable length shift register with the following design goals:
  • A. The length can vary from 3 to 5.
  • B. The change in length is synchronous to the clock.
  • C. The bit depth of the shift register is one bit (design the circuit to handle one bit in and one bit out.)
  • D. Use D-type flip-flops and the minimum amount of combinational logic necessary.
  • E. The register has a mode where the output is a 0.
• 2. Using 4-bit binary counters with parallel load as in Figure 8-27, design a circuit that counts from 8 up to 38 and repeats.
• 3. For the following circuit complete the following table:
  
  
  

  Time	Reset'	Sin	Register A	Register B	FA-C	FA-S
  T0	0	-
  T1	1	0	0000	0000	0	0
  T2	1	1	0000
  T3	1	1	1000
  T4	1	0	1100
  T5	1	0
  T6	1	1
  T7	1	1
  T8	1	0
  T9	1	0
  T10	1	1
  T11	1	0
  T12	1	0
  T13	1	1
  T14	1	0
  T15	1	0
  T16	1	0
  T17	1	0
  T18	1	0
  T19	1	0
  T20	1	0

  
  4. For the circuit given below, determine the output, Q, for 12 clock cycles starting with Q = 00110111.

  

• 5. Design a 4-bit register, with left and right serial inputs, and parallel outputs that has the following functions:
  
  

  Mode Control   S1  S0	Register Operation
  0   0	Add Three
  0   1	Shift Left
  1   0	Complement
  1   1	Shift Right

  
  
• 6. Design a 6 bit ripple counter using Toggle flip-flops. What is the maximum operating frequency of the counter if the propagation delay is 6 nS, the hold time is 1 nS, the setup time is 3 nS, and all bits must be stable for 6 nS?