Introduction to Digital Logic and Computer Design

Chapter 7 homework:

• 1. Use the Xilinx tools to simulate the circuit below or work the problem by hand. If possible, do both.

  

  The latches in the above circuit are SR latches (see figure 7-10a) and a D latch (see figure 7-12b) with control.

  If using the Xilinx software, you will need to add a master reset to each flip-flop so that you can start it in a known condition. The flip-flops in your simulation must start in the reset state. Use the following input signals for C, J, and K.

  

  If simulating the circuits by hand, show the S input of the slave SR latch and the Q output of each latch as a minimum.

  Here is a D type flip flop with reset written in VHDL that you can use as a guide to writing your descriptions if you decide to use the Xilinx tools to simulate the circuits.

• 2. Demonstrate and explain the "1's catching", mentioned on page 539, for the Master Slave JK flip-flop.
• 3. Figure 7-12a shows a D latch based on NAND gates and one inverter. Design a D latch based on NOR gates and the minimum amount of additonal logic to create a D latch with the same function table as shown in Figure 7-12b.
• 4. Analyze the circuit below and derive the state table and state diagram.

  

• 5. Design a Moore model circuit (where the output can change only on a positive clock edge) that detects the bit pattern 1010111 (least significant bit first). This pattern can be detected even if it overlaps. Use a D-type flip-flop for the output detection bit (goes 1 when the pattern is detected, 0 otherwise). Use a JK-type flip-flop for the most significant state bit. Use a Toggle-type flip-flop for the next most significant bit and D-type flip-flops for any others. Show a state table, state diagram, how you simplified the logic to sum-of-products or product-of-sums, and draw a circuit.
• 6. The following sequential circuit has a 4 bit bus, X, going into a bank of 4 D-type flip-flops. The output of the flip-flops are connected to the inputs of a 4 bit 2's complementer circuit with carry lookahead (see homework solution 6-14). The 4 output bits of the 2's complementer are connected to a bank of 4 D-type flip-flops. All of the flip-flops share a common clock signal. What is the maximum clock frequency of this circuit? The flip-flop setup time is 8 nS, hold time is 2 nS, and propagation delay is 4 nS. The propagation delay of the XOR gate is 4 nS and OR gates have a propagation delay of 3 nS?

  

  

• 7. Replace the 4 bit 2's complementer circuit with carry lookahead shown in homework problem 6 with a 4 bit 2's complementer circuit using 2-input 2-output cells (see homework solution 6-13) connected in cascade with lines similar to a carry between them. What is the maximum clock frequency of this circuit? Draw the circuit.

• 8. Design, in VHDL, a special AB flip-flop with two outputs that has the following characteristic table:

  

• 9. Derive an excitation table for the AB flip-flop in problem 8.
• 10. Write the VHDL code for problems 6 and 7. Compare both circuits and verify that they are functionally equivalent by stimulating the inputs to the circuits with identical inputs.