This contribution discusses the requirements of ATM Available Bit Rate switch algorithms, and demonstrates how each of these requirements can be tested. As a case study, the performance of the ERICA switch algorithm [1] is evaluated and the effect of some features and options of the algorithm is examined. The requirements tested include: efficiency, delay, fairness, transient and steady state performance, scalability, and adaptation to variable capacity and various source traffic models. The performance of the algorithm is evaluated for various configurations and background traffic patterns.

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