Computer
Architecture
Announcements:
Updated 12/16/2018
Chapter 7 problem 4.F with the 2 CLB solution has an error. The o0 output
of the Switch Matrix should be 10. (Or the D3 input should go to the m3 input
of the Switch Matrix).
The maximum size gray code counter on problem 4.G with the 4 CLB is 3-bits.
Updated 12/15/2018
The solution on problem 1 of the exam 3 practice problems has been updated
to show the correct use of flip-flops. The previous solution used an older
version of the CLB where the mux inputs were labeled differntly.
The solution to problem 4.G on the chapter 7 homework has an issue with the
4 CLB version. The problem is stated that there must be a count enable and
reset. The largest size counter is 2-bits. Same as the 2 CLB solution. If
count enable and reset were removed from the problem statement, a 3-bit
(corrected) gray code counter is the largest size counter.
If you have a conflict with the final exam start time of 5:30, you may start
the exam at 6:00 and go to 8:00.
Updated 11/27/2018
The final exam time has changed to 5:30 to 7:30 on Monday December 17th.
Updated 11/18/2018
Chapter 7 and 8 problems and solutions have been posted.
The Exam 3 study notes is posted.
Past Exam 3 problems is posted.
Updated 11/11/2018
Corrections to Chapter 6 problems and solutions. I corrected the numbering on the problems. I corrected the solution for problem 11B.
Updated 10/30/2018
The Exam 2 study notes is posted.
Past Exam 2 problems is posted.
Chapter 6 problems and solutions have been posted.
Updated 10/12/2018
Chapter 5 problems and solutions have been posted.
Updated 09/25/2018
The Exam 1 study notes is posted.
Past Exam 1 problems is posted.
Chapter 4 problems and solutions have been posted.
Updated 09/12/2018
Chapter 3 problems and solutions have been posted.
Updated 09/05/2018
The solution for problem 7 in the chapter 1 homework has been corrected.
The solution for problem 5c in the chapter 2 homework has been corrected.
Updated 08/29/2018
You can find the Boolean Algebra
identities here. Identities 1 through 17 will be provided on quizzes
and exams.
Updated 08/28/2018
Introduction notes have been corrected.
Updated 08/27/2018
Introduction, chapter 1, and chapter 2 notes have been posted.
Chapters 1 and 2 problems and solutions have been posted.
Course Description:
Digital computers and digital information-processing systems; Boolean
algebra, principles and methodology of logical design; machine language
programming; register transfer logic; microprocessor hardware, software,
and interfacing; fundamentals of digital circuits and systems; computer
organization and control; memory systems; arithmetic unit design.
Occasional laboratory exercises.
Course Information:
- Prerequisite:
- Time:Monday, Wednesday 5:30 - 7:00
- Place:Sever 102
- Texts: Digital Design with RTL Design, VHDL and Verilog,
2nd Edition by Frank Vahid
- Professor: Tom Jolley, jolley@seas.wustl.edu
- TA:TBD
- Grading: Homework 0%, Quizes 25%, 3 Exams 25% each
Class Procedures:
- If you are going to miss class, please let me know via email. This
way I can let you know about any important changes in the class schedule.
- When you miss class, you are still responsible for the material covered
in class. I recommend that you have someone pick up the class handouts for
you and make a copy of the notes they take. I will not provide copies of my
lecture material other than what you find on this web site.
- Since I don't have office hours, you can send email to me if you have
problems with homework or other questions related to this course.
- There is a lot of material to cover in a short period of time and not
all topics will be covered at the depth desired in class. Therefore, it is
essential that you read the book, do the homework, and review the
handouts given in class.
- All exams will be closed book. More specifics on the exams will be
given in class.
- If you suspect the class may be canceled due to weather, please call
the Joint Engineering office at Washington University or call me. We will
follow Washington University's snow schedule, not UMSL's.