Computer Architecture

Chapter 7 Solutions:

• 1. A 4Mx8 DRAM memory device must have every row refreshed within 4 mS. The device has 4096 words per row. It takes 400 nS to refresh a row. What is the minimum percentage of time the DRAM is unavailable due to refresh?
  
  4096 words per row is the same as 4096 columns per row. A 4Mx8 DRAM with 4096 columns will have 1024 rows (4096*1024 = 4M). Since it takes 400nS to refresh one row and there are 1024 rows, it will take 400nS * 1024 = 409.6uS to refresh all rows. Therefore, the minimum percentage of time the DRAM is unavailable is (409.6uS/4mS) * 100 = 10.24%.
• 2. Show the truth table for a ROM designed as a SIN(angle) Look-Up-Table. The angle is an 8 bit value with the least significant bit equal to 90.0/255 degrees. The output is an 8 bit value with the least significant bit equal to 1.0/128.0. Only show the truth table for addresses 120 to 140.
  
  All 0's on the input is 0 degrees and all 1's, 255, on the input is 90.0 degrees.
  

  Address	Angle	Data	Sin(Angle)
  120	42.3529	86	0.673696
  121	42.7059	86	0.678235
  122	43.0588	87	0.682749
  123	43.4118	87	0.687237
  124	43.7647	88	0.691698
  125	44.1176	89	0.696134
  126	44.4706	89	0.700543
  127	44.8235	90	0.704926
  128	45.1765	90	0.709281
  129	45.5294	91	0.713610
  130	45.8824	91	0.717912
  131	46.2353	92	0.722186
  132	46.5882	92	0.726434
  133	46.9412	93	0.730653
  134	47.2941	94	0.734845
  135	47.6471	94	0.739009
  136	48.000	95	0.743145
  137	48.3529	95	0.747253
  138	48.7059	96	0.751332
  139	49.0588	96	0.755383
  140	49.4118	97	0.759405

• 3. A memory circuit is to be designed to hold a video image that has been sampled at 8 bits per picture element (pixel). The image size is 640x480 pixels. How many 64Kx1 SRAMs will it take to hold the video image?
  
  Each bit plane will need five 64Kx1 SRAMS from (640*480)/65536 rounded up. Since there are 8 bit planes the circuit will need 5*8 = 40 64Kx1 SRAMs.
• 4. For the two FPGA circuits, FPGA CLB and FPGA with 4 CLBs, Is it possible to map the following:
  • A. A register? What is the largest size?
  • B. A multiplexer? What is the largest size?
  • C. A decoder? What is the largest size?
  • D. A counter? What is the largest size?
  • E. A Full Adder? How many full adders?
  • F. A Priority Encoder? What size?
  • G. A Gray code counter with enable and reset? How many bits?
  • H. What is the largest size odd function? An XOR is a two-input odd function.
  
  Using the FPGA CLB

  Circuit	Yes/No	Largest Size/Number of bits	FPGA CLB circuit
  A	Yes	2 bits
  B	Yes	2 to 1
  C	Yes	1 to 2 line (with enable)
  D	Yes	2 bits
  E	Yes	1 Full Adder
  F	Yes	4 to 2 (without valid)
  G	Yes	2 bits
  H	Yes	5 bits

  
  Using the FPGA with 4 CLBs

  Circuit	Yes/No	Largest Size/Number of bits	FPGA 4 CLB circuit
  A	Yes	4 bits
  B	Yes	4 to 1
  C	Yes	2 to 4 line with enable
  D	Yes	4 bits
  E	Yes	2 Full Adders
  F	Yes	4 to 2 (with valid)
  G	Yes	3 bits
  H	Yes	9 bits

• 5. The FPGA CLB we have been using in class only shows the programmable flow of data. Design a circuit that implements an FPGA CLB. See the description of how the FPGA CLB is programmed in figure 7.31 of the course book. You may use multi-bit registers and flip-flops with load, multiplexers, and the minimum amount of additional combinational logic. Consider using a hierarchical design where you design smaller components, such as a CLB, and use the components in the top level schematic.
  Schematic for one CLB.
  
  Schematic for switch matrix.
  
  Schematic for FPGA using CLB and switch matrix components.