Computer Architecture

Chapter 7 Problems:

• 1. A 4Mx8 DRAM memory device must have every row refreshed within 4 mS. The device has 4096 words per row. It takes 400 nS to refresh a row. What is the minimum percentage of time the DRAM is unavailable due to refresh?
• 2. Show the truth table for a ROM designed as a SIN(angle) Look-Up-Table. The angle is an 8 bit value with the least significant bit equal to 90.0/255 degrees. The output is an 8 bit value with the least significant bit equal to 1.0/128.0. Only show the truth table for addresses 120 to 140.
• 3. A memory circuit is to be designed to hold a video image that has been sampled at 8 bits per picture element (pixel). The image size is 640x480 pixels. How many 64Kx1 SRAMs will it take to hold the video image?
• 4. For the two FPGA circuits, FPGA CLB and FPGA with 4 CLBs, Is it possible to map the following:
  • A. A register? What is the largest size?
  • B. A multiplexer? What is the largest size?
  • C. A decoder? What is the largest size?
  • D. A counter? What is the largest size?
  • E. A Full Adder? How many full adders?
  • F. A Priority Encoder? What size?
  • G. A Gray code counter with enable and reset? How many bits?
  • H. What is the largest size odd function? An XOR is a two-input odd function.
• 5. The FPGA CLB we have been using in class only shows the programmable flow of data. Design a circuit that implements an FPGA CLB. See the description of how the FPGA CLB is programmed in figure 7.31 of the course book. You may use multi-bit registers and flip-flops with load, multiplexers, and the minimum amount of additional combinational logic. Consider using a hierarchical design where you design smaller components, such as a CLB, and use the components in the top level schematic.