Computer Architecture

Section 2 Problems:

• 1. Evaluate the given Boolean functions for the variable values given
  • A. X = (a + b)(c + d) given a = 1, b = 1, c = 0, d = 0
  • B. Y = a + b * c + d given a = 0, b = 1, c = 0, d = 0
  • C. Z = a * b * c * d' + a' * b * c * d' + a' * b' * c * d given a = 0, b = 1, c = 1, d = 0
• 2. Draw logic circuits that directly implement the following functions using logic gates. Do not simplify the equations.
  • A. X = AB + A'B'
  • B. Y = a + (b + (c + d))
  • C. Z = abc' + a'bc + a'b'c
  • D. W = mn + m'no + p
• 3. Prove the following theorems using Boolean algebraic manipulation using the basic Boolean algebra postulates
  • A. X + X * Y = X
  • B. X * (X + Y) = X
  • C. X * Y + X * Y' = X
  • D. (X + Y) * (X + Y') = X
  • E. X * Y + X' * Z + Y * Z = X * Y + X' * Z
  • F. (X + Y) * (X' + Z) * (Y + Z) = (X + Y) * (X' + Z)
• 4. Vahid 2.11
• 5. Vahid 2.17
• 6. Vahid 2.20
• 7. Vahid 2.27
• 8. Vahid 2.28
• 9. Vahid 2.29
• 10. Vahid 2.30
• 11. Vahid 2.31
• 12. Vahid 2.34
• 13. Vahid 2.48
• 14. Vahid 2.49
• 15. Vahid 2.52
• 16. Vahid 2.58. Implement as a sum of minterms.
• 17. Vahid 2.69
• 18. Design a 4 to 16 line decoder using 2 to 4 line decoders and the minimum amount of additional combinational logic.
• 19. Design a 16 to 1 multiplexer using 4 to 1 multiplexers and the minimum amount of additional combinational logic.
• 20. Using a 4 to 16 line decoder and one OR gate, design a circuit that implements problem 15 (Vahid 2.58).
• 21. Using an 8 to 1 multiplexer and one NOT gate, design a circuit that implements problem 15 (Vahid 2.58).
• 22. Using AND, OR, NAND, NOR, and NOT logic gates, design a 4 to 2 line priority encoder with a valid output.