Difference between revisions of "Lecture Notes"
From CSE460t Wiki
Jump to navigationJump to search| Line 10: | Line 10: | ||
*[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] | *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] | ||
*[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] | *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] | ||
| + | *[[media:P145-cong.pdf|Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays]] | ||
*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
Revision as of 15:30, 26 January 2012
- Standard Cell Example
- Espresso Example
- Espresso Example Output
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 2
- VHDL Example 2 Synthesized RTL Schematic
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic
- Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
