Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx45
Project ID (random number) b6923f38c9fe4ea1a634511a3de9716d.7C8BB87729244D8C9D156853FBAA7B73.2 Target Package: csg324
Registration ID 210641303_1777494432_210566142_247 Target Speed: -3
Date Generated 2015-01-21T10:16:42 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Xeon(R) CPU X5690 @ 3.47GHz CPU Speed 3458 MHz
CPU Name Intel(R) Xeon(R) CPU X5690 @ 3.47GHz CPU Speed 3458 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Xeon(R) CPU X5690 @ 3.47GHz CPU Speed 3458 MHz
CPU Name Intel(R) Xeon(R) CPU X5690 @ 3.47GHz CPU Speed 3458 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 24-bit up counter=1
  • 27-bit up counter=1
FSMs=1 Multiplexers=2
  • 8-bit 2-to-1 multiplexer=1
  • 8-bit 7-to-1 multiplexer=1
Registers=79
  • Flip-Flops=79
MiscellaneousStatistics
  • AGG_BONDED_IO=30
  • AGG_IO=30
  • AGG_LOCED_IO=30
  • AGG_SLICE=110
  • NUM_BONDED_IOB=30
  • NUM_BSFULL=199
  • NUM_BSLUTONLY=66
  • NUM_BSREGONLY=99
  • NUM_BSUSED=364
  • NUM_BUFG=2
  • NUM_ILOGIC2=3
  • NUM_IOB_FF=3
  • NUM_LOCED_IOB=30
  • NUM_LOGIC_O5ANDO6=76
  • NUM_LOGIC_O5ONLY=57
  • NUM_LOGIC_O6ONLY=82
  • NUM_LUT_RT_DRIVES_CARRY4=5
  • NUM_LUT_RT_DRIVES_FLOP=45
  • NUM_LUT_RT_EXO5=45
  • NUM_LUT_RT_EXO6=5
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=57
  • NUM_RAMB8BWER=2
  • NUM_SLICEL=37
  • NUM_SLICEX=73
  • NUM_SLICE_CARRY4=35
  • NUM_SLICE_CONTROLSET=18
  • NUM_SLICE_CYINIT=412
  • NUM_SLICE_F7MUX=2
  • NUM_SLICE_FF=370
  • NUM_SLICE_UNUSEDCTRL=17
  • NUM_UNUSABLE_FF_BELS=54
  • Xilinx Core fifo_generator_v9_3, Xilinx CORE Generator 14.7=2
NetStatistics
  • NumNets_Active=529
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=12
  • NumNodesOfType_Active_BOUNCEIN=77
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=10
  • NumNodesOfType_Active_CLKPIN=93
  • NumNodesOfType_Active_CLKPINFEED=16
  • NumNodesOfType_Active_CNTRLPIN=41
  • NumNodesOfType_Active_DOUBLE=460
  • NumNodesOfType_Active_GENERIC=55
  • NumNodesOfType_Active_GLOBAL=80
  • NumNodesOfType_Active_INPUT=92
  • NumNodesOfType_Active_IOBIN2OUT=42
  • NumNodesOfType_Active_IOBOUTPUT=39
  • NumNodesOfType_Active_LUTINPUT=762
  • NumNodesOfType_Active_OUTBOUND=496
  • NumNodesOfType_Active_OUTPUT=486
  • NumNodesOfType_Active_PADINPUT=25
  • NumNodesOfType_Active_PADOUTPUT=16
  • NumNodesOfType_Active_PINBOUNCE=323
  • NumNodesOfType_Active_PINFEED=945
  • NumNodesOfType_Active_PINFEED2=3
  • NumNodesOfType_Active_QUAD=394
  • NumNodesOfType_Active_REGINPUT=169
  • NumNodesOfType_Active_SINGLE=614
  • NumNodesOfType_Gnd_BOUNCEIN=16
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_HGNDOUT=6
  • NumNodesOfType_Gnd_INPUT=80
  • NumNodesOfType_Gnd_OUTBOUND=3
  • NumNodesOfType_Gnd_OUTPUT=4
  • NumNodesOfType_Gnd_PINBOUNCE=19
  • NumNodesOfType_Gnd_PINFEED=74
  • NumNodesOfType_Gnd_SINGLE=2
  • NumNodesOfType_Vcc_HVCCOUT=47
  • NumNodesOfType_Vcc_LUTINPUT=134
  • NumNodesOfType_Vcc_PINFEED=134
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=17
  • IOB-IOBS=13
  • SLICEL-SLICEM=12
  • SLICEX-SLICEL=14
  • SLICEX-SLICEM=13
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=35
  • FF_SR=72
  • HARD0=8
  • HARD1=8
  • ILOGIC2=3
  • ILOGIC2_IFF=3
  • IOB=30
  • IOB_IMUX=21
  • IOB_INBUF=21
  • IOB_OUTBUF=17
  • LUT5=179
  • LUT6=220
  • PAD=30
  • RAMB8BWER=2
  • RAMB8BWER_RAMB8BWER=2
  • REG_SR=298
  • SELMUX2_1=5
  • SLICEL=37
  • SLICEX=73
 
Configuration Data
FF_SR
  • CK=[CK:72] [CK_INV:0]
  • SRINIT=[SRINIT0:72]
  • SYNC_ATTR=[ASYNC:72]
ILOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:3]
ILOGIC2_IFF
  • CLK0=[CLK0_INV:0] [CLK0:3]
  • IFFTYPE=[FF:3]
  • SRINIT_Q=[0:3]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:17]
  • SLEW=[SLOW:17]
  • SUSPEND=[3STATE:17]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • DATA_WIDTH_A=[9:2]
  • DATA_WIDTH_B=[9:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • EN_RSTRAM_A=[TRUE:2]
  • EN_RSTRAM_B=[TRUE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
REG_SR
  • CK=[CK:298] [CK_INV:0]
  • LATCH_OR_FF=[FF:298]
  • SRINIT=[SRINIT0:287] [SRINIT1:11]
  • SYNC_ATTR=[ASYNC:298]
SLICEL
  • CLK=[CLK:23] [CLK_INV:0]
SLICEX
  • CLK=[CLK:70] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
CARRY4
  • CIN=22
  • CO0=8
  • CO3=22
  • CYINIT=13
  • DI0=35
  • DI1=23
  • DI2=22
  • DI3=22
  • O0=19
  • O1=19
  • O2=15
  • O3=14
  • S0=35
  • S1=27
  • S2=23
  • S3=22
FF_SR
  • CE=18
  • CK=72
  • D=72
  • Q=72
HARD0
  • 0=8
HARD1
  • 1=8
ILOGIC2
  • CLK0=3
  • D=3
  • Q4=3
ILOGIC2_IFF
  • CLK0=3
  • D=3
  • Q1=3
IOB
  • I=21
  • O=17
  • PAD=30
  • T=8
IOB_IMUX
  • I=21
  • OUT=21
IOB_INBUF
  • OUT=21
  • PAD=21
IOB_OUTBUF
  • IN=17
  • OUT=17
  • TRI=8
LUT5
  • A1=9
  • A2=11
  • A3=28
  • A4=46
  • A5=39
  • O5=179
LUT6
  • A1=37
  • A2=95
  • A3=115
  • A4=205
  • A5=153
  • A6=215
  • O6=220
PAD
  • PAD=30
RAMB8BWER
  • ADDRAWRADDR0=2
  • ADDRAWRADDR1=2
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR2=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR0=2
  • ADDRBRDADDR1=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR2=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI10=2
  • DIADI11=2
  • DIADI12=2
  • DIADI13=2
  • DIADI14=2
  • DIADI15=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIADI8=2
  • DIADI9=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI10=2
  • DIBDI11=2
  • DIBDI12=2
  • DIBDI13=2
  • DIBDI14=2
  • DIBDI15=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIBDI8=2
  • DIBDI9=2
  • DIPADIP0=2
  • DIPADIP1=2
  • DIPBDIP0=2
  • DIPBDIP1=2
  • DOBDO0=2
  • DOBDO1=2
  • DOBDO2=2
  • DOBDO3=2
  • DOBDO4=2
  • DOBDO5=2
  • DOBDO6=2
  • DOBDO7=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=2
  • ADDRAWRADDR1=2
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR2=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR0=2
  • ADDRBRDADDR1=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR2=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI10=2
  • DIADI11=2
  • DIADI12=2
  • DIADI13=2
  • DIADI14=2
  • DIADI15=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIADI8=2
  • DIADI9=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI10=2
  • DIBDI11=2
  • DIBDI12=2
  • DIBDI13=2
  • DIBDI14=2
  • DIBDI15=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIBDI8=2
  • DIBDI9=2
  • DIPADIP0=2
  • DIPADIP1=2
  • DIPBDIP0=2
  • DIPBDIP1=2
  • DOBDO0=2
  • DOBDO1=2
  • DOBDO2=2
  • DOBDO3=2
  • DOBDO4=2
  • DOBDO5=2
  • DOBDO6=2
  • DOBDO7=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
REG_SR
  • CE=146
  • CK=298
  • D=298
  • Q=298
SELMUX2_1
  • 0=5
  • 1=2
  • OUT=5
  • S0=5
SLICEL
  • A2=16
  • A3=16
  • A4=35
  • A5=16
  • A6=35
  • AMUX=8
  • AQ=22
  • AX=3
  • B=1
  • B2=8
  • B3=9
  • B4=28
  • B5=9
  • B6=24
  • BQ=22
  • BX=3
  • C2=10
  • C3=10
  • C4=25
  • C5=11
  • C6=24
  • CE=15
  • CIN=22
  • CLK=23
  • CMUX=3
  • COUT=22
  • CQ=19
  • CX=6
  • D=1
  • D2=10
  • D3=11
  • D4=25
  • D5=12
  • D6=25
  • DMUX=1
  • DQ=18
  • DX=4
SLICEX
  • A=16
  • A1=20
  • A2=24
  • A3=39
  • A4=45
  • A5=46
  • A6=41
  • AMUX=25
  • AQ=67
  • AX=41
  • B=16
  • B1=10
  • B2=17
  • B3=19
  • B4=29
  • B5=32
  • B6=26
  • BMUX=21
  • BQ=55
  • BX=45
  • C=4
  • C1=12
  • C2=12
  • C3=16
  • C4=23
  • C5=27
  • C6=22
  • CE=26
  • CLK=70
  • CMUX=15
  • CQ=50
  • CX=32
  • D=12
  • D1=2
  • D2=5
  • D3=12
  • D4=17
  • D5=23
  • D6=18
  • DMUX=14
  • DQ=45
  • DX=35
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_compxlibgui 1 1 0 0 0 0 0
_impact 3 2 0 0 0 0 0
bitgen 13 13 0 0 0 0 0
cse_server 1 1 0 0 0 0 0
edif2ngd 5 5 0 0 0 0 0
map 21 17 0 0 0 0 0
netgen 12 12 0 0 0 0 0
ngcbuild 7 7 0 0 0 0 0
ngdbuild 28 28 0 0 0 0 0
par 17 17 0 0 0 0 0
trce 17 17 0 0 0 0 0
xst 53 50 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-01-20T21:56:33
PROP_intWbtProjectID=7C8BB87729244D8C9D156853FBAA7B73 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=csg324
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_COREGEN=1
FILE_UCF=1 FILE_VERILOG=1
FILE_VHDL=1
 
Core Statistics
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=64 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=4
c_axis_tstrb_width=4 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=0
c_count_type=0 c_data_count_width=10 c_default_value=BlankString c_din_width=8
c_din_width_axis=1 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=8
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan6 c_full_flags_rst_val=0 c_has_almost_empty=0
c_has_almost_full=0 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=0 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=0 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=0 c_preload_regs=1
c_prim_fifo_type=1kx18 c_prog_empty_thresh_assert_val=4 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_negate_val=5 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=1022
c_prog_full_type=0 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=10 c_rd_depth=1024 c_rd_freq=1 c_rd_pntr_width=10
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=0 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=10
c_wr_depth=1024 c_wr_depth_axis=1024 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=10 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=2 NGDBUILD_NUM_FD=213 NGDBUILD_NUM_FDE=164 NGDBUILD_NUM_GND=5
NGDBUILD_NUM_IBUF=6 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=62
NGDBUILD_NUM_LUT2=51 NGDBUILD_NUM_LUT3=19 NGDBUILD_NUM_LUT4=59 NGDBUILD_NUM_LUT5=21
NGDBUILD_NUM_LUT6=35 NGDBUILD_NUM_MUXCY=102 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=9
NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=67
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=213 NGDBUILD_NUM_FDE=164 NGDBUILD_NUM_GND=5
NGDBUILD_NUM_IBUF=19 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=62
NGDBUILD_NUM_LUT2=51 NGDBUILD_NUM_LUT3=19 NGDBUILD_NUM_LUT4=59 NGDBUILD_NUM_LUT5=21
NGDBUILD_NUM_LUT6=35 NGDBUILD_NUM_MUXCY=102 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=9
NGDBUILD_NUM_OBUFT=8 NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=3
NGDBUILD_NUM_XORCY=67
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx45-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5