USBCommOnAtlys Project Status (01/21/2015 - 10:16:50)
Project File: USBCommOnAtlys.xise Parser Errors: No Errors
Module Name: USBCommOnAtlys Implementation State: Programming File Generated
Target Device: xc6slx45-3csg324
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
71 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 370 54,576 1%  
    Number used as Flip Flops 370      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 265 27,288 1%  
    Number used as logic 215 27,288 1%  
        Number using O6 output only 82      
        Number using O5 output only 57      
        Number using O5 and O6 76      
        Number used as ROM 0      
    Number used as Memory 0 6,408 0%  
    Number used exclusively as route-thrus 50      
        Number with same-slice register load 45      
        Number with same-slice carry load 5      
        Number with other load 0      
Number of occupied Slices 110 6,822 1%  
Number of MUXCYs used 140 13,644 1%  
Number of LUT Flip Flop pairs used 364      
    Number with an unused Flip Flop 66 364 18%  
    Number with an unused LUT 99 364 27%  
    Number of fully used LUT-FF pairs 199 364 54%  
    Number of unique control sets 18      
    Number of slice register sites lost
        to control set restrictions
54 54,576 1%  
Number of bonded IOBs 30 218 13%  
    Number of LOCed IOBs 30 30 100%  
    IOB Flip Flops 3      
Number of RAMB16BWERs 0 116 0%  
Number of RAMB8BWERs 2 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 3 376 1%  
    Number used as ILOGIC2s 3      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.44      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jan 21 10:14:21 2015062 Warnings (0 new)23 Infos (15 new)
Translation ReportCurrentWed Jan 21 10:14:43 2015000
Map ReportCurrentWed Jan 21 10:15:53 201501 Warning (0 new)8 Infos (0 new)
Place and Route ReportCurrentWed Jan 21 10:16:14 201507 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentWed Jan 21 10:16:22 2015003 Infos (0 new)
Bitgen ReportCurrentWed Jan 21 10:16:41 201501 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Jan 21 10:16:43 2015
WebTalk Log FileCurrentWed Jan 21 10:16:50 2015

Date Generated: 01/21/2015 - 10:25:11