**************************************** Report : area Design : opticalflow Version: J-2014.09-SP5 Date : Fri Oct 28 13:01:34 2016 **************************************** Library(s) Used: vtvt_tsmc180 (File: /project/linuxlab/cadence/vendors/VTVT/vtvt_tsmc180/Synopsys_Libraries/libs/vtvt_tsmc180.db) Number of ports: 523 Number of nets: 48530 Number of cells: 46070 Number of combinational cells: 42255 Number of sequential cells: 3815 Number of macros/black boxes: 0 Number of buf/inv: 4302 Number of references: 44 Combinational area: 2150425.836039 Buf/Inv area: 122343.624659 Noncombinational area: 666501.802582 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 2816927.638620 Total area: undefined 1 **************************************** Report : reference Design : opticalflow Version: J-2014.09-SP5 Date : Fri Oct 28 13:01:34 2016 **************************************** Attributes: b - black box (unknown) bo - allows boundary optimization d - dont_touch mo - map_only h - hierarchical n - noncombinational r - removable s - synthetic operator u - contains unmapped logic Reference Library Unit Area Count Total Area Attributes ----------------------------------------------------------------------------- ab_or_c_or_d vtvt_tsmc180 82.668602 17 1405.366234 and2_1 vtvt_tsmc180 51.029999 4283 218561.484772 and2_2 vtvt_tsmc180 51.029999 30 1530.899963 and2_4 vtvt_tsmc180 55.112400 7 385.786800 and3_1 vtvt_tsmc180 55.112400 11 606.236401 and4_1 vtvt_tsmc180 64.297798 9 578.680183 buf_1 vtvt_tsmc180 45.926998 87 3995.648838 buf_2 vtvt_tsmc180 45.926998 45 2066.714916 buf_4 vtvt_tsmc180 55.112400 6 330.674400 dksp_1 vtvt_tsmc180 266.376587 4 1065.506348 n dp_1 vtvt_tsmc180 174.522598 3780 659695.421448 n dp_2 vtvt_tsmc180 183.707993 29 5327.531784 n dp_4 vtvt_tsmc180 192.893402 1 192.893402 n drp_1 vtvt_tsmc180 220.449600 1 220.449600 n fulladder vtvt_tsmc180 202.078796 2239 452454.425110 r inv_1 vtvt_tsmc180 27.774900 3961 110016.380629 inv_2 vtvt_tsmc180 27.774900 170 4721.733074 inv_4 vtvt_tsmc180 36.741600 33 1212.472801 mux2_1 vtvt_tsmc180 73.483200 1325 97365.240097 mux2_2 vtvt_tsmc180 73.483200 8 587.865601 nand2_1 vtvt_tsmc180 36.741600 7589 278832.002678 nand2_2 vtvt_tsmc180 36.741600 102 3747.643204 nand2_4 vtvt_tsmc180 55.112400 7 385.786800 nand3_1 vtvt_tsmc180 45.926998 784 36006.766541 nand3_2 vtvt_tsmc180 45.926998 1 45.926998 nand4_1 vtvt_tsmc180 55.112400 23 1267.585201 nand4_2 vtvt_tsmc180 55.112400 2 110.224800 nor2_1 vtvt_tsmc180 36.741600 17076 627399.562225 nor2_2 vtvt_tsmc180 36.741600 19 698.090401 nor2_4 vtvt_tsmc180 64.297798 5 321.488991 nor3_1 vtvt_tsmc180 45.926998 72 3306.743866 nor3_2 vtvt_tsmc180 45.926998 1 45.926998 nor4_1 vtvt_tsmc180 55.112400 30 1653.372002 nor4_2 vtvt_tsmc180 55.112400 1 55.112400 not_ab_or_c_or_d vtvt_tsmc180 64.297798 98 6301.184219 or2_1 vtvt_tsmc180 45.926998 1649 75733.619930 or2_2 vtvt_tsmc180 45.926998 8 367.415985 or2_4 vtvt_tsmc180 55.112400 2 110.224800 or3_1 vtvt_tsmc180 64.297798 19 1221.658165 or4_1 vtvt_tsmc180 64.297798 4 257.191193 xnor2_1 vtvt_tsmc180 91.853996 751 68982.351204 xnor2_2 vtvt_tsmc180 91.853996 57 5235.677788 xor2_1 vtvt_tsmc180 82.668602 1596 131939.088776 xor2_2 vtvt_tsmc180 82.668602 128 10581.581055 ----------------------------------------------------------------------------- Total 44 references 2816927.638620 1