****************************************
Report : area
Design : BitcoinBlockHashing
Version: J-2014.09-SP5
Date   : Wed Oct 26 17:54:29 2016
****************************************

Library(s) Used:

    vtvt_tsmc180 (File: /project/linuxlab/cadence/vendors/VTVT/vtvt_tsmc180/Synopsys_Libraries/libs/vtvt_tsmc180.db)

Number of ports:                           92
Number of nets:                         51322
Number of cells:                        49940
Number of combinational cells:          38269
Number of sequential cells:             11671
Number of macros/black boxes:               0
Number of buf/inv:                       2061
Number of references:                      22

Combinational area:            2079281.275244
Buf/Inv area:                    66392.727041
Noncombinational area:         2036853.244370
Macro/Black Box area:                0.000000
Net Interconnect area:      undefined  (No wire load specified)

Total cell area:               4116134.519613
Total area:                 undefined
1
 
****************************************
Report : reference
Design : BitcoinBlockHashing
Version: J-2014.09-SP5
Date   : Wed Oct 26 17:54:29 2016
****************************************

Attributes:
    b - black box (unknown)
   bo - allows boundary optimization
    d - dont_touch
   mo - map_only
    h - hierarchical
    n - noncombinational
    r - removable
    s - synthetic operator
    u - contains unmapped logic

Reference          Library       Unit Area   Count    Total Area   Attributes
-----------------------------------------------------------------------------
ab_or_c_or_d       vtvt_tsmc180
                                 82.668602     189  15624.365776  
and2_1             vtvt_tsmc180
                                 51.029999     135   6889.049835  
and3_1             vtvt_tsmc180
                                 55.112400       8    440.899200  
and4_1             vtvt_tsmc180
                                 64.297798      24   1543.147156  
buf_1              vtvt_tsmc180
                                 45.926998     504  23147.207062  
dp_1               vtvt_tsmc180
                                174.522598   11671  2036853.244370
                                                                  n
fulladder          vtvt_tsmc180
                                202.078796    1333  269371.035583 r
inv_1              vtvt_tsmc180
                                 27.774900    1557  43245.519979  
mux2_1             vtvt_tsmc180
                                 73.483200    9804  720429.293518 
mux2_4             vtvt_tsmc180
                                 82.668602       1     82.668602  
nand2_1            vtvt_tsmc180
                                 36.741600   17294  635409.231033 
nand3_1            vtvt_tsmc180
                                 45.926998    1744  80096.684753  
nand4_1            vtvt_tsmc180
                                 55.112400    2235  123176.214123 
nor2_1             vtvt_tsmc180
                                 36.741600    1719  63158.810463  
nor3_1             vtvt_tsmc180
                                 45.926998      58   2663.765892  
nor4_1             vtvt_tsmc180
                                 55.112400     447  24635.242825  
not_ab_or_c_or_d   vtvt_tsmc180
                                 64.297798     225  14467.004585  
or2_1              vtvt_tsmc180
                                 45.926998     736  33802.270630  
or3_1              vtvt_tsmc180
                                 64.297798       4    257.191193  
or4_1              vtvt_tsmc180
                                 64.297798       4    257.191193  
xnor2_1            vtvt_tsmc180
                                 91.853996       9    826.685966  
xor2_1             vtvt_tsmc180
                                 82.668602     239  19757.795876  
-----------------------------------------------------------------------------
Total 22 references                                 4116134.519613
1