Administrative stuff
The instructor for the course this semester is Michael Hall. Office hours offered are listed below. If you want to make an appointment with me, contact me on Piazza. I am also available immediately after class if requested.
The text of the welcome email that I sent to the class on Mon., Aug. 19, is here.
The teaching assistants this semester are Zaid Ahmed and Evin Jaff.
We are combining office hours for CSE 560M and CSE 362M. For content questions only, Prof. Roger Chamberlain is also offering office hours.
Class lectures are generally from 5:30pm to 7pm (technically 6:50pm) on Mondays and Wednesdays. The location is Green Hall L0120.
We will primarily use Piazza for communication in the class. Please use Piazza over email for asking questions. The link for the class is here.
We will use Canvas for submitting assignments and for recording/viewing of grades. The link for the class is here.
Partners are allowed on the simulation assignments. See the guidelines here.
Office hours
| Name | Days | Time | Location | Special Notes |
|---|---|---|---|---|
| Michael Hall | Monday, Wednesday | 3:00 PM - 4:00 PM | Green Hall 3155 | Instructor; Available after class by request and also by appointment |
| Roger Chamberlain | Tuesday, Thursday | 4:00 PM - 5:00 PM | McKelvey 1053 | Content-only questions |
| Zaid Ahmed | Friday | 10:00 AM - 12:00 PM | Online (Zoom) | TA |
| Evin Jaff | Sunday | 12:00 PM - 2:00 PM | Online (Zoom) | TA |
Calendar (subject to revision at any time)
- Aug 26 Introduction
Lecture slides (full), video
- Aug 28 Instruction Set Architecture (ISA)
Lecture slides (full), video - Sep 2 Labor Day (no class)
- Sep 4 Instruction Set Architecture (ISA)
Lecture slides (full), video - Sep 9 Performance
Lecture slides (full), video
- Sep 11 Performance Modeling
Lecture slides (full), video - Sep 16 Pipelining
Lecture slides (full) (updated), video (up to pipelining multi-cycle operations)
- Sep 18 Branch Prediction
Lecture slides (full), video - Sep 23 Technology
Lecture slides (full) (updated), video (up to reliability)
- Sep 25 Superscalar
Lecture slides (full) video - Sep 30 Static Scheduling
Lecture slides (full) (updated), video (up to data-level parallelism)
- Oct 2 Dynamic Scheduling
Lecture slides (full) (updated) video - Oct 7 Fall Break (no class)
- Oct 9 Dynamic Scheduling
Lecture slides (full), video (includes review for exam 1 at the end) - Oct 14 Dynamic Scheduling and Review for Exam 1
Dynamic Scheduling slides (full), Review slides (full), video
- Oct 16 Exam 1
- Oct 21 Caches
Lecture slides (full), video
- Oct 23 Caches
Lecture slides (full), video (up to write propagation) - Oct 28 Virtual Memory
Lecture slides (full), video
- Oct 30 Virtual Memory
Lecture slides (full), video - Nov 4 Multithreading
Lecture slides (full), video
- Nov 6 Spectre/Meltdown
Lecture slides (full) (updated), video - Nov 11 Security
Lecture slides (full) (updated), video (JumpSwitches video is not showing), JumpSwitches conference talk
- Nov 13 Multicores
Lecture slides (full), video - Nov 18 Multicores
Lecture slides (full), video
- Nov 20 Multicores
Lecture slides (full), video - Nov 25 Domain-Specific Accelerators
Lecture slides (full), video
- Nov 27 Thanksgiving Break (no class)
- Dec 2 Multiprocessors and Review for Exam 2
Lecture slides (full) (updated), Exam Review slides (full) (updated), video - Dec 4 Exam 2 (We'll finish up today, no final.)
Reading
The optional text for the course is Jean-Loup Baer, Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors, Cambridge University Press, 2010.
- Introduction - Baer, Section 1.1
- Performance - Baer, Sections 1.2-1.4 (except 1.3.2)
- Performance Modeling - Baer, Section 1.3.2
- Learning gem5
- A Linux tutorial put together by Joshua Glatt.
- Gem5 tutorial video
- Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood, "The gem5 simulator," SIGARCH Comput. Archit. News 39(2):1-7, August 2011. DOI=10.1145/2024716.2024718.
- gem5 Documentation
- Pipelining - Baer, Section 2.1
- Branch Prediction - Baer, Section 4.1
- Technology - Baer, Section 9.1
- Superscalar - Baer, Sections 3.1, 3.2, 3.5.1
- Static Scheduling - Baer, Sections 3.3.1-3.3.4, 7.5
- Dynamic Scheduling - Baer, Sections 5.0-5.2, 5.3.3, 5.4-5.5
- Caches - Baer, Sections 2.2, 6.1-6.3.1
- Virtual Memory - Baer, Sections 2.3, 6.1.1
- Multithreading - Baer, Section 8.1
- Nadav Amit, Fred Jacobs, and Michael Wei, "JumpSwitches: Restoring the Performance of Indirect Branches In the Era of Spectre," in Proc. of USENIX Annual Technical Conference, 2019.
- Multicores - Baer, Sections 7.0, 7.1.3, 7.2-7.4, 8.2
- Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, and John Hennessy, "The directory-based cache coherence protocol for the DASH multiprocessor," in Proc. of 17th ACM International Symposium on Computer Architecture (ISCA), pp. 148-159, 1990, doi:10.1145/325164.325132
- Anthony M. Cabrera, Clayton J. Faber, Kyle Cepeda, Robert Derber, Cooper Epstein, Jason Zheng, Ron K. Cytron, and Roger D. Chamberlain, "DIBS: A Data Integration Benchmark Suite," in Proc. of ACM/SPEC International Conference on Performance Engineering Companion (ICPE), April 2018, pp. 25-28. DOI: 10.1145/3185768.3186307.
- H.T. Kung, "Why Systolic Architectures?," Computer, 15(1):37-46, January 1982, doi:10.1109/MC.1982.1653825
- Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence," in Proc. of 18th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 87-94, 2010, doi:10.1109/FCCM.2010.22
- Norman P. Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," in Proc. of IEEE International Symposium on Computer Architecture (ISCA), pp. 1-12, 2017, doi:10.1145/3079856.3080246
- Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, and David Brooks, "Automatically accelerating non-numerical programs by architecture-compiler co-design," Commun. ACM 60(12):88-97, December 2017, doi:10.1145/3139461
- Simple RISC-V 3-stage Pipeline in Chisel
Assignments
- Practice Problem Set #1, and solution.
- Practice Problem Set #2, and solution.
- Sep 11 Assignment #1, due Sep. 20, 2024.
- Practice Problem Set #3, and solution.
- Sep 23 Assignment #2, due Oct. 11, 2024.
- Practice Problem Set #4, and solution.
- Practice Problem Set #5, and solution.
- Practice Problem Set #6, and solution.
- Oct 14 Assignment #3, due Nov. 1, Nov. 22, and Dec. 3, 2024.
- Oct 21 Assignment #4, due Nov. 8, 2024.
- Practice Problem Set #7, and solution.
- Practice Problem Set #8, and solution.
- Nov 11 Assignment #5, due Dec. 6, 2024.
- Practice Problem Set #9, and solution.
Last modified 2 December 2024.
Michael Hall <mhall24 AT wustl.edu>