Syllabus

SPRING 2018

LECTURE	DATE	TOPICS	PREPARATION	ASSIGNED	DUE
1	JAN 19	Course Introduction Number Systems Base Conversion Arithmetic Operations Codes	Course Introduction Chapter 1 The Reflected Binary (Gray) Code	Homework 1
2	JAN 26	Boolean Algebra DeMorgan's Theorem The Consensus Theorem Introduction to K-Maps	Chapter 2
6	FEB 2	Boole's Expansion Theorem (Second Pass) Introduction to Xilinx 7-Series FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX)	Boole's Expansion Theorem Chapter 5 Xilinx 7-Series FPGAs Overview Xilinx 7-Series CLB User Guide Xilinx 7-Series DC/AC Switching Characteristics
7	FEB 9	Digilent Nexys4 DDR Development Board Digilent Nexys4 DDR Board Schematic (LEDs, Switches) Concepts of VCCIO and Core Voltage	Digilent Nexys4 DDR Manual Digilent Nexys4 DDR Schematics Lab #1 Introduction Finding Your .bit File	Lab 1	Homework 3
8	FEB 16	Implementing Functions with NAND and NOR Gates Implementing Functions with Decoders The Priority Encoder The 4-bit Adder as a 2-Level Circuit Addition and Subtraction of 2s Complement Numbers Incrementing (The Incrementer Circuit) Multiplication by Constants	Chapter 3
9	FEB 23	Gate Propogation Delay Races and Hazards Review	Chapter 2		Lab 1
14	MAR 2	FSM Timging/Max Clock Rate Path Analysis and Timing Equivalent States Minimizing Completely Specified Machines Combination Mealy/Moore Machines Contact Bounce	Chapter 4 Path Analysis and Timing Vivado Clock Constraints Tutorial Definitions and Theorems for Sequential Machines Minimizing Completely Specified Machines Contact Bounce	Lab 2
15	MAR 9	Digital Systems = Datapath + Control Register Transfers Tri-State Buffers Pull-ups/Pull-downs The Bus-Based Difference Engine	Chapter 6 The Difference Engine	Homework 6	Homework 5
	MAR 16	SPRING BREAK
16	MAR 23	The Bus-Based Difference Engine Datapath VHDL Shift Registers Parallel-to-Serial Conversion Serial-to-Parallel Conversion Ripple Counters	Chapter 6 The Difference Engine	Lab 3	Lab 2
17	MAR 30	The Bus-Based Difference Engine Control FSM VHDL	The Difference Engine	Homework 6
20	APR 6	The Really Simple RISC Computer Simple Synchronous Static RAM Introduction to Assembly Language and Hand Assembly	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem RSRC/SRC SIMULATOR	Homework 7
21	APR 13	The Difference Engine in RSRC Assembly Language RSRC Instruction Fetch RTN ADD RTN Datapath Refinement RSRC Control FSM VHDL	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC Abstract RTN
22	APR 20	Displacement-Based Addressing Branch Instruction Datapath Refinement Shift Instruction Datapath Refinement	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC/SRC Displacement-Based Addressing	Homework 8	Homework 7
23	APR 27	R[rc] Multiplexor Design RSRC ALU VHDL 1Kx32 RSRC Memory Subsystem Memory: 6T SRAM Cell DRAM Cell	Chapter 7 The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem