Syllabus

SPRING 2018

LECTURE	DATE	TOPICS	PREPARATION	ASSIGNED	DUE
1	JAN 17	Course Introduction Number Systems Base Conversion Arithmetic Operations Codes	Course Introduction Chapter 1 The Reflected Binary (Gray) Code	Homework 1
2	JAN 22	Boolean Algebra DeMorgan's Theorem The Consensus Theorem Introduction to K-Maps	Chapter 2
3	JAN 24	Standard Forms: Ʃ Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder	Chapter 2 Chapter 3	Homework 2	Homework 1
4	JAN 29	Essential Prime Implicants and Optimized Expressions Standard Forms: Π Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The 74LS04 Inverter The Mux The Decoder Implementing Circuits Using Muxes	Chapter 2 Chapter 3 74LS04 Datasheet
5	JAN 31	Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass)	Standard Cell Circuit VHDL Tutorial Vivado Tutorial Boole's Expansion Theorem	Homework 3	Homework 2
6	FEB 5	Boole's Expansion Theorem (Second Pass) Introduction to Xilinx 7-Series FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX)	Boole's Expansion Theorem Chapter 5 Xilinx 7-Series FPGAs Overview Xilinx 7-Series CLB User Guide Xilinx 7-Series DC/AC Switching Characteristics
7	FEB 7	Digilent Nexys4 DDR Development Board Digilent Nexys4 DDR Board Schematic (LEDs, Switches) Concepts of VCCIO and Core Voltage	Digilent Nexys4 DDR Manual Digilent Nexys4 DDR Schematics Lab #1 Introduction Finding Your .bit File	Lab 1	Homework 3
8	FEB 12	Implementing Functions with NAND and NOR Gates Implementing Functions with Decoders The Priority Encoder The 4-bit Adder as a 2-Level Circuit Addition and Subtraction of 2s Complement Numbers Incrementing (The Incrementer Circuit) Multiplication by Constants	Chapter 3
9	FEB 14	Gate Propogation Delay Races and Hazards Review	Chapter 2		Lab 1
10	FEB 19	EXAM 1
11	FEB 21	Oscillators and Clock Distribution Flip-Flop as a Black Box A First Counter (Incrementer + FFs) The Difference Engine (DE) VHDL for FFs, Registers, Counters, and The DE Setup Time Hold Time Clock-to-Output Time Introduction to Metastability	Chapter 4 Oscillators and Clock Distribution First Counter VHDL Tutorial The Difference Engine Anomalous Behavior of Synchronizer and Arbiter Circuits Measured Flip-Flop Responses to Marginal Triggering	Homework 4
12	FEB 26	Latches NOR SR Latch VHDL Flip-Flops 74LS74/74S74 Flip-Flop Formal Definition of Mealy- and Moore-Model FSMs State Tables Second Counter: FSM Design Example Clocks in VHDL	Chapter 4 NOR SR Latch VHDL 74LS74 Datasheet Second Counter Vivado Simulation Tutorial 2 (Forcing a Clock)
13	FEB 28	Sequence Recognizer FSMs in VHDL State Assignment One-Hot FSM Implementation Recognizing Character Sequences (Packet Sniffing)	Chapter 4 VHDL Tutorial Sequence Detector 4-3	Homework 5	Homework 4
14	MAR 5	FSM Timging/Max Clock Rate Path Analysis and Timing Equivalent States Minimizing Completely Specified Machines Combination Mealy/Moore Machines Contact Bounce	Chapter 4 Path Analysis and Timing Vivado Clock Constraints Tutorial Definitions and Theorems for Sequential Machines Minimizing Completely Specified Machines Contact Bounce	Lab 2
15	MAR 7	Digital Systems = Datapath + Control Register Transfers Tri-State Buffers Pull-ups/Pull-downs The Bus-Based Difference Engine	Chapter 6 The Difference Engine	Homework 6	Homework 5
	MAR 12	SPRING BREAK
	MAR 14	SPRING BREAK
16	MAR 19	The Bus-Based Difference Engine Datapath VHDL Shift Registers Parallel-to-Serial Conversion Serial-to-Parallel Conversion Ripple Counters	Chapter 6 The Difference Engine	Lab 3	Lab 2
17	MAR 21	The Bus-Based Difference Engine Control FSM VHDL	The Difference Engine	Homework 6
18	MAR 26	Review			Lab 3
19	MAR 28	Exam 2
20	APR 2	The Really Simple RISC Computer Simple Synchronous Static RAM Introduction to Assembly Language and Hand Assembly	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem RSRC/SRC SIMULATOR	Homework 7
21	APR 4	The Difference Engine in RSRC Assembly Language RSRC Instruction Fetch RTN ADD RTN Datapath Refinement RSRC Control FSM VHDL	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC Abstract RTN
22	APR 9	Displacement-Based Addressing Branch Instruction Datapath Refinement Shift Instruction Datapath Refinement	The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC/SRC Displacement-Based Addressing	Homework 8	Homework 7
23	APR 11	R[rc] Multiplexor Design RSRC ALU VHDL 1Kx32 RSRC Memory Subsystem Memory: 6T SRAM Cell DRAM Cell	Chapter 7 The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem
24	APR 16	A Commercial EPROM A Commercial SRAM A Commercial DRAM The Concept of Cache RSRC VHDL and Simulation Testbench	AMD 32Kx8 EPROM Datasheet Cypress 32Kx8 SRAM Micron 4Mx16 EDO DRAM Micron 8 Gb DDR4 DRAM The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC VHDL Supplied by the Instructor	Homework 9	Homework 8
25	APR 18	1-Bus vs. 2-Bus vs. 3-Bus RSRC 3-Bus RSRC Register File Basic Pipelined SRC/RSRC Intel 8086 Bus Architecture RSRC Instruction Set Review RSRC Architecture Review	1-Bus SRC Block Diagram (From Heuring and Jordan) 2-Bus SRC Block Diagram (From Heuring and Jordan) 3-Bus SRC Block Diagram (From Heuring and Jordan) 3-Bus SRC Register File (From Heuring and Jordan) Basic Pipelined SRC/RSRC Intel 8086 Block Diagram The Really Simple RISC Computer (RSRC) The RSRC Instruction Set
26	APR 23	Difference Engine in C (x86) w/Assembly Review	Difference Engine in C (x86)		Homework 9
27	APR 25	Exam 3