Lecture Notes

• VHDL Lecture
• State Equal Output Moore Machine Example
• Anomalous Behavior of Synchronizer and Arbiter Circuits
• Measured Flip-Flop Responses to Marginal Triggering
• VHDL Lecture
• CPLD Timing 1
• CPLD Timing 2
• Metastability 1
• Metastability 2
• IEEE Code of Ethics
• Employment Contract

Links:

Agile Solutions

Xilinx Timing Model

Xilinx Tool Flow Article by Core Technologies

ACM Code of Ethics

USB Ultrasound Probe

Commercial Fetal Doppler Unit

Commercial Fetal Doppler Unit

Pulsed Doppler Fundamentals