General Information

Instructor, William D. Richard, Ph.D., 538 Jolley Hall, 314-935-4676, wdr@wustl.edu

Office Hours: Monday and Wednesday, 9:00-11:00 a.m. or by appointment

Course Web Page: http://classes.engineering.wustl.edu/cse462/index.php/Main_Page

Text: NA (You should have access to a VHDL reference.)

Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Lopata Hall Room 202

Exam #1: February 23, 2016

Final Exam: May 10, 2016

Project Presentations: April 28, 2016 (in class)

Paper Due: April 29, 2016 by 5 p.m.

Grading: Two exams, 20% each. Homework: 10%. Project: 50%.

Homework: Homework will be assigned weekly prior to the first exam. Homework turned in at the start of class on the due date will be graded by the instructor. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.