Difference between revisions of "Syllabus"

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(Replaced content with "{| class="wikitable" |+SPRING 2018 |- |LECTURE |DATE |TOPICS |PREPARATION |ASSIGNED |DUE |- |1 |JAN 19 |Course Introduction | | | |- |2 |JAN 26 | | | | |- |6 |FEB 2 | |...")
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|JAN 19
 
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|Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes
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|Course Introduction
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|[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]]
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|Homework 1
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|JAN 26
 
|JAN 26
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|Boolean Algebra<br />DeMorgan's Theorem<br />The Consensus Theorem<br />Introduction to K-Maps
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|[[media:Mano_ch02_images.pdf|Chapter 2]]
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|FEB 2
 
|FEB 2
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|Boole's Expansion Theorem (Second Pass)<br />Introduction to Xilinx 7-Series FPGAs<br />USING LUTs to Implement Logic (LUT = Storage + MUX)<br />
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|[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]<br />[[media:Mano_ch05_images.pdf|Chapter 5]]<br />[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]]<br />[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]]<br />[[media:Ds181_Artix_7_Data_Sheet.pdf|Xilinx 7-Series DC/AC Switching Characteristics]]
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|FEB 9
 
|FEB 9
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|Digilent Nexys4 DDR Development Board<br />Digilent Nexys4 DDR Board Schematic (LEDs, Switches)<br />Concepts of VCCIO and Core Voltage
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|[[media:Dev_Board_Manual.pdf|Digilent Nexys4 DDR Manual]]<br />[[media:Dev_Board_Schematics.pdf|Digilent Nexys4 DDR Schematics]]<br />[[media:Lab_1_Introduction.pdf|Lab #1 Introduction]]<br />[[media:FINDING_YOUR_DOT_BIT_FILE.pdf|Finding Your .bit File]]
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|Lab 1
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|Homework 3
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|FEB 16
 
|FEB 16
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|Implementing Functions with NAND and NOR Gates<br />Implementing Functions with Decoders<br />The Priority Encoder<br />The 4-bit Adder as a 2-Level Circuit<br />Addition and Subtraction of 2s Complement Numbers<br />Incrementing (The Incrementer Circuit)<br />Multiplication by Constants
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|[[media:Mano_ch03_images.pdf|Chapter 3]]
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|FEB 23
 
|FEB 23
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|Gate Propogation Delay<br />Races and Hazards<br />Review
 
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|[[media:Mano_ch02_images.pdf|Chapter 2]]
 
 
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|Lab 1
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|14
 
|14
 
|MAR 2
 
|MAR 2
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|FSM Timging/Max Clock Rate<br />Path Analysis and Timing<br />Equivalent States<br />Minimizing Completely Specified Machines<br />Combination Mealy/Moore Machines<br />Contact Bounce
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|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Path_Analysis_and_Timing.pdf|Path Analysis and Timing]]<br />[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial]<br />[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]]<br />[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]]<br />[https://www.allaboutcircuits.com/textbook/digital/chpt-4/contact-bounce/ Contact Bounce]
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|Lab 2
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|15
 
|MAR 9
 
|MAR 9
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|Digital Systems = Datapath + Control<br />Register Transfers<br />Tri-State Buffers<br />Pull-ups/Pull-downs<br />The Bus-Based Difference Engine
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|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]]
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|Homework 6
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|Homework 5
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|MAR 23
 
|MAR 23
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|The Bus-Based Difference Engine Datapath VHDL<br />Shift Registers<br />Parallel-to-Serial Conversion<br />Serial-to-Parallel Conversion<br />Ripple Counters
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|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]]
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|Lab 3
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|Lab 2
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|MAR 30
 
|MAR 30
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|The Bus-Based Difference Engine Control FSM VHDL<br />
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|[[media:The_Difference_Engine.pdf|The Difference Engine]]
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|Homework 6
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|APR 6
 
|APR 6
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|The Really Simple RISC Computer<br />Simple Synchronous Static RAM<br />Introduction to Assembly Language and Hand Assembly
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|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]<br />[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar RSRC/SRC SIMULATOR]
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|Homework 7
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|APR 13
 
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|The Difference Engine in RSRC Assembly Language<br />RSRC Instruction Fetch RTN<br />ADD RTN<br />Datapath Refinement<br />RSRC Control FSM VHDL
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|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]]
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|APR 20
 
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|Displacement-Based Addressing<br />Branch Instruction Datapath Refinement<br />Shift Instruction Datapath Refinement
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|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]]
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|Homework 8
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|Homework 7
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|APR 27
 
|APR 27
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|R[rc] Multiplexor Design<br />RSRC ALU VHDL<br />1Kx32 RSRC Memory Subsystem<br />Memory: 6T SRAM Cell<br />DRAM Cell
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|PROJECT PRESENTATIONS
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|[[media:Mano_ch07_images.pdf|Chapter 7]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]
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Revision as of 18:54, 19 December 2017

SPRING 2018
LECTURE DATE TOPICS PREPARATION ASSIGNED DUE
1 JAN 19 Course Introduction
2 JAN 26
6 FEB 2
7 FEB 9
8 FEB 16
9 FEB 23
14 MAR 2
15 MAR 9
MAR 16 SPRING BREAK
16 MAR 23
17 MAR 30
20 APR 6
21 APR 13
22 APR 20
23 APR 27 PROJECT PRESENTATIONS
Retrieved from "http://classes.engineering.wustl.edu/cse462/index.php?title=Syllabus&oldid=977"