Difference between revisions of "Syllabus"
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|Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes | |Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes | ||
|[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] | |[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] | ||
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|Boolean Algebra<br />DeMorgan's Theorem<br />The Consensus Theorem<br />Introduction to K-Maps | |Boolean Algebra<br />DeMorgan's Theorem<br />The Consensus Theorem<br />Introduction to K-Maps | ||
|[[media:Mano_ch02_images.pdf|Chapter 2]] | |[[media:Mano_ch02_images.pdf|Chapter 2]] | ||
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|Boole's Expansion Theorem (Second Pass)<br />Introduction to Xilinx 7-Series FPGAs<br />USING LUTs to Implement Logic (LUT = Storage + MUX)<br /> | |Boole's Expansion Theorem (Second Pass)<br />Introduction to Xilinx 7-Series FPGAs<br />USING LUTs to Implement Logic (LUT = Storage + MUX)<br /> | ||
|[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]<br />[[media:Mano_ch05_images.pdf|Chapter 5]]<br />[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]]<br />[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]]<br />[[media:Ds181_Artix_7_Data_Sheet.pdf|Xilinx 7-Series DC/AC Switching Characteristics]] | |[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]<br />[[media:Mano_ch05_images.pdf|Chapter 5]]<br />[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]]<br />[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]]<br />[[media:Ds181_Artix_7_Data_Sheet.pdf|Xilinx 7-Series DC/AC Switching Characteristics]] | ||
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|Digilent Nexys4 DDR Development Board<br />Digilent Nexys4 DDR Board Schematic (LEDs, Switches)<br />Concepts of VCCIO and Core Voltage | |Digilent Nexys4 DDR Development Board<br />Digilent Nexys4 DDR Board Schematic (LEDs, Switches)<br />Concepts of VCCIO and Core Voltage | ||
|[[media:Dev_Board_Manual.pdf|Digilent Nexys4 DDR Manual]]<br />[[media:Dev_Board_Schematics.pdf|Digilent Nexys4 DDR Schematics]]<br />[[media:Lab_1_Introduction.pdf|Lab #1 Introduction]]<br />[[media:FINDING_YOUR_DOT_BIT_FILE.pdf|Finding Your .bit File]] | |[[media:Dev_Board_Manual.pdf|Digilent Nexys4 DDR Manual]]<br />[[media:Dev_Board_Schematics.pdf|Digilent Nexys4 DDR Schematics]]<br />[[media:Lab_1_Introduction.pdf|Lab #1 Introduction]]<br />[[media:FINDING_YOUR_DOT_BIT_FILE.pdf|Finding Your .bit File]] | ||
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|Implementing Functions with NAND and NOR Gates<br />Implementing Functions with Decoders<br />The Priority Encoder<br />The 4-bit Adder as a 2-Level Circuit<br />Addition and Subtraction of 2s Complement Numbers<br />Incrementing (The Incrementer Circuit)<br />Multiplication by Constants | |Implementing Functions with NAND and NOR Gates<br />Implementing Functions with Decoders<br />The Priority Encoder<br />The 4-bit Adder as a 2-Level Circuit<br />Addition and Subtraction of 2s Complement Numbers<br />Incrementing (The Incrementer Circuit)<br />Multiplication by Constants | ||
|[[media:Mano_ch03_images.pdf|Chapter 3]] | |[[media:Mano_ch03_images.pdf|Chapter 3]] | ||
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|Gate Propogation Delay<br />Races and Hazards<br />Review | |Gate Propogation Delay<br />Races and Hazards<br />Review | ||
|[[media:Mano_ch02_images.pdf|Chapter 2]] | |[[media:Mano_ch02_images.pdf|Chapter 2]] | ||
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|Lab 1 | |Lab 1 | ||
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|FSM Timging/Max Clock Rate<br />Path Analysis and Timing<br />Equivalent States<br />Minimizing Completely Specified Machines<br />Combination Mealy/Moore Machines<br />Contact Bounce | |FSM Timging/Max Clock Rate<br />Path Analysis and Timing<br />Equivalent States<br />Minimizing Completely Specified Machines<br />Combination Mealy/Moore Machines<br />Contact Bounce | ||
|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Path_Analysis_and_Timing.pdf|Path Analysis and Timing]]<br />[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial]<br />[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]]<br />[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]]<br />[https://www.allaboutcircuits.com/textbook/digital/chpt-4/contact-bounce/ Contact Bounce] | |[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Path_Analysis_and_Timing.pdf|Path Analysis and Timing]]<br />[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial]<br />[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]]<br />[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]]<br />[https://www.allaboutcircuits.com/textbook/digital/chpt-4/contact-bounce/ Contact Bounce] | ||
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|Digital Systems = Datapath + Control<br />Register Transfers<br />Tri-State Buffers<br />Pull-ups/Pull-downs<br />The Bus-Based Difference Engine | |Digital Systems = Datapath + Control<br />Register Transfers<br />Tri-State Buffers<br />Pull-ups/Pull-downs<br />The Bus-Based Difference Engine | ||
|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]] | |[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]] | ||
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|SPRING BREAK | |SPRING BREAK | ||
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|The Bus-Based Difference Engine Datapath VHDL<br />Shift Registers<br />Parallel-to-Serial Conversion<br />Serial-to-Parallel Conversion<br />Ripple Counters | |The Bus-Based Difference Engine Datapath VHDL<br />Shift Registers<br />Parallel-to-Serial Conversion<br />Serial-to-Parallel Conversion<br />Ripple Counters | ||
|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]] | |[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]] | ||
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|The Bus-Based Difference Engine Control FSM VHDL<br /> | |The Bus-Based Difference Engine Control FSM VHDL<br /> | ||
|[[media:The_Difference_Engine.pdf|The Difference Engine]] | |[[media:The_Difference_Engine.pdf|The Difference Engine]] | ||
|Homework 6 | |Homework 6 | ||
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|The Really Simple RISC Computer<br />Simple Synchronous Static RAM<br />Introduction to Assembly Language and Hand Assembly | |The Really Simple RISC Computer<br />Simple Synchronous Static RAM<br />Introduction to Assembly Language and Hand Assembly | ||
|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]<br />[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar RSRC/SRC SIMULATOR] | |[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]<br />[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar RSRC/SRC SIMULATOR] | ||
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|The Difference Engine in RSRC Assembly Language<br />RSRC Instruction Fetch RTN<br />ADD RTN<br />Datapath Refinement<br />RSRC Control FSM VHDL | |The Difference Engine in RSRC Assembly Language<br />RSRC Instruction Fetch RTN<br />ADD RTN<br />Datapath Refinement<br />RSRC Control FSM VHDL | ||
|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]] | |[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]] | ||
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|Displacement-Based Addressing<br />Branch Instruction Datapath Refinement<br />Shift Instruction Datapath Refinement | |Displacement-Based Addressing<br />Branch Instruction Datapath Refinement<br />Shift Instruction Datapath Refinement | ||
|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]] | |[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]] | ||
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|R[rc] Multiplexor Design<br />RSRC ALU VHDL<br />1Kx32 RSRC Memory Subsystem<br />Memory: 6T SRAM Cell<br />DRAM Cell | |R[rc] Multiplexor Design<br />RSRC ALU VHDL<br />1Kx32 RSRC Memory Subsystem<br />Memory: 6T SRAM Cell<br />DRAM Cell | ||
|[[media:Mano_ch07_images.pdf|Chapter 7]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]] | |[[media:Mano_ch07_images.pdf|Chapter 7]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]] | ||
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Revision as of 18:51, 19 December 2017
LECTURE | DATE | TOPICS | PREPARATION | ASSIGNED | DUE |
1 | JAN 19 | Course Introduction Number Systems Base Conversion Arithmetic Operations Codes |
Course Introduction Chapter 1 The Reflected Binary (Gray) Code |
Homework 1 | |
2 | JAN 26 | Boolean Algebra DeMorgan's Theorem The Consensus Theorem Introduction to K-Maps |
Chapter 2 | ||
6 | FEB 2 | Boole's Expansion Theorem (Second Pass) Introduction to Xilinx 7-Series FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX) |
Boole's Expansion Theorem Chapter 5 Xilinx 7-Series FPGAs Overview Xilinx 7-Series CLB User Guide Xilinx 7-Series DC/AC Switching Characteristics |
||
7 | FEB 9 | Digilent Nexys4 DDR Development Board Digilent Nexys4 DDR Board Schematic (LEDs, Switches) Concepts of VCCIO and Core Voltage |
Digilent Nexys4 DDR Manual Digilent Nexys4 DDR Schematics Lab #1 Introduction Finding Your .bit File |
Lab 1 | Homework 3 |
8 | FEB 16 | Implementing Functions with NAND and NOR Gates Implementing Functions with Decoders The Priority Encoder The 4-bit Adder as a 2-Level Circuit Addition and Subtraction of 2s Complement Numbers Incrementing (The Incrementer Circuit) Multiplication by Constants |
Chapter 3 | ||
9 | FEB 23 | Gate Propogation Delay Races and Hazards Review |
Chapter 2 | Lab 1 | |
14 | MAR 2 | FSM Timging/Max Clock Rate Path Analysis and Timing Equivalent States Minimizing Completely Specified Machines Combination Mealy/Moore Machines Contact Bounce |
Chapter 4 Path Analysis and Timing Vivado Clock Constraints Tutorial Definitions and Theorems for Sequential Machines Minimizing Completely Specified Machines Contact Bounce |
Lab 2 | |
15 | MAR 9 | Digital Systems = Datapath + Control Register Transfers Tri-State Buffers Pull-ups/Pull-downs The Bus-Based Difference Engine |
Chapter 6 The Difference Engine |
Homework 6 | Homework 5 |
MAR 16 | SPRING BREAK | ||||
16 | MAR 23 | The Bus-Based Difference Engine Datapath VHDL Shift Registers Parallel-to-Serial Conversion Serial-to-Parallel Conversion Ripple Counters |
Chapter 6 The Difference Engine |
Lab 3 | Lab 2 |
17 | MAR 30 | The Bus-Based Difference Engine Control FSM VHDL |
The Difference Engine | Homework 6 | |
20 | APR 6 | The Really Simple RISC Computer Simple Synchronous Static RAM Introduction to Assembly Language and Hand Assembly |
The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem RSRC/SRC SIMULATOR |
Homework 7 | |
21 | APR 13 | The Difference Engine in RSRC Assembly Language RSRC Instruction Fetch RTN ADD RTN Datapath Refinement RSRC Control FSM VHDL |
The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC Abstract RTN |
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22 | APR 20 | Displacement-Based Addressing Branch Instruction Datapath Refinement Shift Instruction Datapath Refinement |
The Really Simple RISC Computer (RSRC) The RSRC Instruction Set RSRC/SRC Displacement-Based Addressing |
Homework 8 | Homework 7 |
23 | APR 27 | R[rc] Multiplexor Design RSRC ALU VHDL 1Kx32 RSRC Memory Subsystem Memory: 6T SRAM Cell DRAM Cell |
Chapter 7 The Really Simple RISC Computer (RSRC) The RSRC Instruction Set 1Kx32 RSRC Memory Subsystem |