Difference between revisions of "Lecture Notes"
From CSE462 Wiki
Jump to navigationJump to search| Line 14: | Line 14: | ||
*[[media:CreatingAnADCUsingFPGAResources.pdf|Lattice Semiconductor ADC White Paper]] | *[[media:CreatingAnADCUsingFPGAResources.pdf|Lattice Semiconductor ADC White Paper]] | ||
*[[media:SAR_ADC_Paper.pdf|Successive Approximation ADC in FPGA Paper]] | *[[media:SAR_ADC_Paper.pdf|Successive Approximation ADC in FPGA Paper]] | ||
| + | *[[media:LTC2000_DAC.pdf|Example 2.5 Gsample/s Current Output DAC]] | ||
*[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Lecture]] | *[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Lecture]] | ||
*[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Machine Example]] | *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Machine Example]] | ||
Revision as of 21:36, 21 January 2015
- Course Introduction
- Use Advanced PCB Technology to Produce 50% Smaller Product Designs
- Reflection Lecture
- Maximum ExpressPCB Trace Impedance
- LVDS Fundamentals
- R-2R DAC Circuit
- R-2R DAC SPICE DECK
- R-2R DAC Simulation
- Understanding Flash ADCs
- Fermilab ADC/TDC in FPGA Paper
- Analog Ramp Generator
- Altera Delta-Sigma ADC in FPGA Paper
- Xilinx Modified Delta-Sigma ADC in FPGA Paper
- Lattice Semiconductor ADC White Paper
- Successive Approximation ADC in FPGA Paper
- Example 2.5 Gsample/s Current Output DAC
- VHDL Lecture
- State Equal Output Moore Machine Example
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
- IEEE Code of Ethics
- Employment Contract
Links:
