Difference between revisions of "Lecture Notes"
From CSE462 Wiki
Jump to navigationJump to search| Line 22: | Line 22: | ||
*[[media:Using_LVDS_Inputs.pdf|Xilinx ISE 14.7 LVDS Input Tutorial]] | *[[media:Using_LVDS_Inputs.pdf|Xilinx ISE 14.7 LVDS Input Tutorial]] | ||
*[[media:Simulation_Tutorial.pdf|Xilinx ISE 14.7 Simulation Tutorial]] | *[[media:Simulation_Tutorial.pdf|Xilinx ISE 14.7 Simulation Tutorial]] | ||
| − | *[[media:Vga.pdf|Xilinx ISE 14.7 Spartan 3E | + | *[[media:Vga.pdf|Xilinx ISE 14.7 Digilent Spartan 3E Board VGA UCF File]] |
| − | *[[media:loopback.pdf|Xilnix ISE 14.7 Spartan 3E | + | *[[media:loopback.pdf|Xilnix ISE 14.7 Digilent Spartan 3E Board Loopback UCF File (Instructor Only)]] |
*[[media:MCS_File_Tutorial.pdf|Xilinx ISE 14.7 MCS File Tutorial]] | *[[media:MCS_File_Tutorial.pdf|Xilinx ISE 14.7 MCS File Tutorial]] | ||
Revision as of 14:14, 4 May 2017
- Use Advanced PCB Technology to Produce 50% Smaller Product Designs
- Reflection Lecture
- Oscillators and Clock Distribution
- Lumped Lecture
- ExpressPCB Board Specifications
- Maximum ExpressPCB Trace Impedance
- VHDL Lecture
- Xilinx ISE 14.7 FIFO Tutorial
- Xilinx ISE 14.7 Dualport RAM Tutorial
- Xilinx ISE 14.7 DCM Tutorial
- Xilinx ISE 14.7 VGA Tutorial
- Xilinx ISE 14.7 LVDS Input Tutorial
- Xilinx ISE 14.7 Simulation Tutorial
- Xilinx ISE 14.7 Digilent Spartan 3E Board VGA UCF File
- Xilnix ISE 14.7 Digilent Spartan 3E Board Loopback UCF File (Instructor Only)
- Xilinx ISE 14.7 MCS File Tutorial
- State Equal Output Moore Machine Example
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
Links:
PCB Trace Impedance Calculator
Xilinx ISE Timing Constraints Strategies
