Difference between revisions of "Lecture Notes"
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*[[media:Using_LVDS_Inputs.pdf|Xilinx ISE 14.7 LVDS Input Tutorial]] | *[[media:Using_LVDS_Inputs.pdf|Xilinx ISE 14.7 LVDS Input Tutorial]] | ||
*[[media:Simulation_Tutorial.pdf|Xilinx ISE 14.7 Simulation Tutorial]] | *[[media:Simulation_Tutorial.pdf|Xilinx ISE 14.7 Simulation Tutorial]] | ||
− | *[[media:Vga.pdf|Spartan 3E VGA UCF File]] | + | *[[media:Vga.pdf|Xilinx ISE 14.7 Spartan 3E Development Board VGA UCF File]] |
− | *[[media:loopback.pdf|Spartan 3E Loopback UCF File (Instructor Only - N/A 2017)]] | + | *[[media:loopback.pdf|Xilnix ISE 14.7 Spartan 3E Development Board Loopback UCF File (Instructor Only - N/A 2017)]] |
− | *[[media:MCS_File_Tutorial.pdf|MCS File Tutorial]] | + | *[[media:MCS_File_Tutorial.pdf|Xilinx ISE 14.7 MCS File Tutorial]] |
Revision as of 13:58, 4 May 2017
- Use Advanced PCB Technology to Produce 50% Smaller Product Designs
- Reflection Lecture
- Oscillators and Clock Distribution
- Lumped Lecture
- VHDL Lecture
- Xilinx ISE 14.7 FIFO Tutorial
- Xilinx ISE 14.7 VGA Tutorial
- Xilinx ISE 14.7 LVDS Input Tutorial
- Xilinx ISE 14.7 Simulation Tutorial
- Xilinx ISE 14.7 Spartan 3E Development Board VGA UCF File
- Xilnix ISE 14.7 Spartan 3E Development Board Loopback UCF File (Instructor Only - N/A 2017)
- Xilinx ISE 14.7 MCS File Tutorial
- State Equal Output Moore Machine Example
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
Links:
PCB Trace Impedance Calculator
Xilinx ISE Timing Constraints Strategies