Difference between revisions of "Syllabus"

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{| class="wikitable"
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|+SPRING 2018
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|+CSE 462M SPRING 20xx
 
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|LECTURE
 
|LECTURE
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|1
 
|1
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|JAN 17
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|JAN 15
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|Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes
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|Course Introduction<br />VGA Video<br />Vivado Clocking Wizard<br />VGA Skeleton VHDL<br />NEXYS4 DDR Dev Board Manual<br />NEXYS4 DDR Dev Board Schematic<br />VHDL Tutorial<br />Xilinx Vivado Tutorial
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|[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]]
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|[[media:CSE_462M_COURSE_INTRODUCTION.pdf|Course Introduction]]<br />[http://www.epanorama.net/documents/pc/vga_timing.html VGA Video]<br />[[media:Vivado_2017_Clocking_Wizard_Totorial.pdf|Vivado Clocking Wizard Tutorial]]<br />[[media:VGA_Skeleton.pdf|VGA VHDL Skeleton]]<br />[[media:Dev_Board_Manual.pdf|Digilent NEXYS 4 DDR Development Board Manual]]<br />[[media:Dev_Board_Schematics.pdf|Digilent NEXYS 4 DDR Development Board Schematics]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Tutorial]]<br />[[media:Vivado_Tutorial.pdf|Xilinx Vivado Tutorial]]
 
|Homework 1
 
|Homework 1
 
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|2
 
|2
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|JAN 22
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|JAN 17
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|Boolean Algebra<br />DeMorgan's Theorem<br />The Consensus Theorem<br />Introduction to K-Maps
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|[[media:Mano_ch02_images.pdf|Chapter 2]]
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|3
 
|3
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|JAN 24
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|JAN 22
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|Standard Forms: &#425; Notation<br />Two-Level Circuit Optimization Using K-Maps<br />Proving Identities Using K-Maps<br />The XOR Gate<br />The Half Adder<br />The Full Adder<br />The Ripple-Carry Adder
+
|Bit-Mapped Displays<br />Vivado Block RAM<br />COE Files<br />PCB Fundamentals<br />CAD Drafting Terminology<br />The ExpressPCB CAD Tool<br />ExpressPCB Board Properties<br />Advanced PCB Concepts
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|[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]]
+
|[[media:Vivado_Block_RAM_Tutorial.pdf|Vivado Block RAM Tutorial]]<br />[[media:Example_COE_File.pdf|Example COE File]]<br />[[media:0714IFD1.pdf|PCB Technology Article]]<br />[[media:Drafting_Manual.pdf|Drafting Manual]]<br />[https://www.amazon.com/Design-Dimensioning-Tolerancing-Bruce-Wilson/dp/1590703286/ref=la_B001K88VV6_1_3?s=books&ie=UTF8&qid=1517585859&sr=1-3 CAD Dimensioning Textbook]<br />[https://www.expresspcb.com/ ExpresPCB CAD Tool]<br />[[media:ExpressPCB-Service-Matrix-12-7-2016.pdf |Express PCB Board Matrix]]<br />[[media:Reflection_Lecture.pdf|Reflection Lecture]]<br />[https://emclab.mst.edu/resources/tools/pcb-trace-impedance-calculator/ MS&T Trace Impedance Calculator]<br />[[media:Maximum_ExpressPCB_Trace_Impedance.pdf|Maximum ExpressPCB Trace Impedance]]
 
|Homework 2
 
|Homework 2
 
|Homework 1
 
|Homework 1
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|4
 
|4
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|JAN 29
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|JAN 24
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|Essential Prime Implicants and Optimized Expressions<br />Standard Forms: &#928; Notation<br />Five- and Six-Variable K-Maps<br />Don’t cares<br />Gate propagation delay<br />The 74LS04 Inverter<br />The Mux<br />The Decoder<br />Implementing Circuits Using Muxes
+
|
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|[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]]<br />[[media:Sn74ls04.pdf|74LS04 Datasheet]]
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|5
 
|5
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|JAN 31
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|JAN 29
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|Standard Cell Implementation of Logic Circuits<br />VHDL: VHSIC Hardware Description Language<br />VHDL Constructs: IF, WHEN, SELECT<br />Xilnix Vivado Tool Suite<br />Boole's Expansion Theorem (First Pass)
+
|Character Displays<br />PCB Power and Ground Considerations<br />Project Gantt Chart
−
|[[media:Standard_Cell.JPG|Standard Cell Circuit]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:Vivado_Tutorial.pdf|Vivado Tutorial]]<br />[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]
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|[[media:Gantt Chart.pdf|Project Gantt Chart]]
 
|Homework 3
 
|Homework 3
 
|Homework 2
 
|Homework 2
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|-
 
|6
 
|6
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|FEB 5
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|JAN 31
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|Boole's Expansion Theorem (Second Pass)<br />Introduction to Xilinx 7-Series FPGAs<br />USING LUTs to Implement Logic (LUT = Storage + MUX)<br />
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|
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|[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]<br />[[media:Mano_ch05_images.pdf|Chapter 5]]<br />[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]]<br />[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]]<br />[[media:Ds181_Artix_7_Data_Sheet.pdf|Xilinx 7-Series DC/AC Switching Characteristics]]
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|7
 
|7
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|FEB 7
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|FEB 5
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|Digilent Nexys4 DDR Development Board<br />Digilent Nexys4 DDR Board Schematic (LEDs, Switches)<br />Concepts of VCCIO and Core Voltage
+
|Semester Project Assignment<br />Semester Project Paper Format<br />FPGA Configuration Concepts<br />FPGA Power Requirements
−
|[[media:Dev_Board_Manual.pdf|Digilent Nexys4 DDR Manual]]<br />[[media:Dev_Board_Schematics.pdf|Digilent Nexys4 DDR Schematics]]<br />[[media:Lab_1_Introduction.pdf|Lab #1 Introduction]]<br />[[media:FINDING_YOUR_DOT_BIT_FILE.pdf|Finding Your .bit File]]
+
|[[media:SPRING_2018_PROJECT_ASSIGNMENT.pdf|Project Assignment]]<br />[[media:SPRING_2018_PAPER.pdf|Paper Requirements]]<br />[[media:ug380.pdf|Xilinx Spartan 6 FPGA Configuration User Guide]]<br />[[media:ds162.pdf|Xilnx Spartan 6 LX Family Switching Characteristics]]
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|Lab 1
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|Semester Project
 
|Homework 3
 
|Homework 3
  
 
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|8
 
|8
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|FEB 7
 +
|TEAM PROJECT
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 +
|-
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|9
 
|FEB 12
 
|FEB 12
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|Implementing Functions with NAND and NOR Gates<br />Implementing Functions with Decoders<br />The Priority Encoder<br />The 4-bit Adder as a 2-Level Circuit<br />Addition and Subtraction of 2s Complement Numbers<br />Incrementing (The Incrementer Circuit)<br />Multiplication by Constants
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|TEAM PROJECT
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|[[media:Mano_ch03_images.pdf|Chapter 3]]
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|
  
 
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|-
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|9
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|10
 
|FEB 14
 
|FEB 14
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|Gate Propogation Delay<br />Races and Hazards<br />Review
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|TEAM PROJECT
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|[[media:Mano_ch02_images.pdf|Chapter 2]]
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|
 +
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|
 
|
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|Lab 1
 
  
 
|-
 
|-
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|10
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|11
 
|FEB 19
 
|FEB 19
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|EXAM 1
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|TEAM PROJECT
 
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|
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|-
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|11
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|12
 
|FEB 21
 
|FEB 21
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|Oscillators and Clock Distribution<br />Flip-Flop as a Black Box<br />A First Counter (Incrementer + FFs)<br />The Difference Engine (DE)<br />VHDL for FFs, Registers, Counters, and The DE<br />Setup Time<br />Hold Time<br />Clock-to-Output Time<br />Introduction to Metastability
+
|TEAM PROJECT
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|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]]<br />[[media:First_Counter.pdf|First Counter]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]]<br />[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]]<br />[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]]
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|Homework 4
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|
  
 
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|12
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|13
 
|FEB 26
 
|FEB 26
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|Latches<br />NOR SR Latch VHDL<br />Flip-Flops<br />74LS74/74S74 Flip-Flop<br />Formal Definition of Mealy- and Moore-Model FSMs<br />State Tables<br />Second Counter: FSM Design Example<br />Clocks in VHDL<br />
+
|TEAM PROJECT
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|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Norlatch.pdf|NOR SR Latch VHDL]]<br />[[media:Sn74ls74a.pdf|74LS74 Datasheet]]<br />[[media:Second_Counter.pdf|Second Counter]]<br />[[media:Vivado_Simulation_Tutorial_2.pdf|Vivado Simulation Tutorial 2 (Forcing a Clock)]]
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|
  
 
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|-
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|13
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|14
 
|FEB 28
 
|FEB 28
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|Sequence Recognizer<br />FSMs in VHDL<br />State Assignment<br />One-Hot FSM Implementation<br />Recognizing Character Sequences (Packet Sniffing)
+
|TEAM PROJECT
−
|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:SEQUENCE_DETECTOR_EXAMPLE_4-3.pdf|Sequence Detector 4-3]]
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−
|Homework 5
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|Homework 4
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|
  
 
|-
 
|-
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|14
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|15
 
|MAR 5
 
|MAR 5
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|FSM Timging/Max Clock Rate<br />Path Analysis and Timing<br />Equivalent States<br />Minimizing Completely Specified Machines<br />Combination Mealy/Moore Machines<br />Contact Bounce
+
|TEAM PROJECT
−
|[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:Path_Analysis_and_Timing.pdf|Path Analysis and Timing]]<br />[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial]<br />[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]]<br />[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]]<br />[https://www.allaboutcircuits.com/textbook/digital/chpt-4/contact-bounce/ Contact Bounce]
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−
|Lab 2
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|
  
 
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|-
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|15
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|16
 
|MAR 7
 
|MAR 7
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|Digital Systems = Datapath + Control<br />Register Transfers<br />Tri-State Buffers<br />Pull-ups/Pull-downs<br />The Bus-Based Difference Engine
+
|TEAM PROJECT
−
|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]]
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|Homework 6
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|Homework 5
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|
  
 
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|16
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|17
 
|MAR 19
 
|MAR 19
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|The Bus-Based Difference Engine Datapath VHDL<br />Shift Registers<br />Parallel-to-Serial Conversion<br />Serial-to-Parallel Conversion<br />Ripple Counters
+
|TEAM PROJECT
−
|[[media:Mano_ch06_images.pdf|Chapter 6]]<br />[[media:The_Difference_Engine.pdf|The Difference Engine]]
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−
|Lab 3
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|Lab 2
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|
  
 
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|-
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|17
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|18
 
|MAR 21
 
|MAR 21
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|The Bus-Based Difference Engine Control FSM VHDL<br />
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|TEAM PROJECT
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|[[media:The_Difference_Engine.pdf|The Difference Engine]]
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|Homework 6
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|18
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|19
 
|MAR 26
 
|MAR 26
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|Review
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|TEAM PROJECT
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|Lab 3
 
  
 
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|19
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|20
 
|MAR 28
 
|MAR 28
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|Exam 2
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|TEAM PROJECT
 
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|20
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|21
 
|APR 2
 
|APR 2
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|The Really Simple RISC Computer<br />Simple Synchronous Static RAM<br />Introduction to Assembly Language and Hand Assembly
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|TEAM PROJECT
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|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]<br />[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar RSRC/SRC SIMULATOR]
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|Homework 7
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|21
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|22
 
|APR 4
 
|APR 4
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|The Difference Engine in RSRC Assembly Language<br />RSRC Instruction Fetch RTN<br />ADD RTN<br />Datapath Refinement<br />RSRC Control FSM VHDL
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|TEAM PROJECT
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|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]]
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|22
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|23
 
|APR 9
 
|APR 9
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|Displacement-Based Addressing<br />Branch Instruction Datapath Refinement<br />Shift Instruction Datapath Refinement
+
|TEAM PROJECT
−
|[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]]
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|Homework 8
+
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|Homework 7
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|
  
 
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|23
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|24
 
|APR 11
 
|APR 11
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|R[rc] Multiplexor Design<br />RSRC ALU VHDL<br />1Kx32 RSRC Memory Subsystem<br />Memory: 6T SRAM Cell<br />DRAM Cell
+
|TEAM PROJECT
−
|[[media:Mano_ch07_images.pdf|Chapter 7]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]
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|24
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|25
 
|APR 16
 
|APR 16
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|A Commercial EPROM<br />A Commercial SRAM<br />A Commercial DRAM<br />The Concept of Cache<br />RSRC VHDL and Simulation Testbench
+
|TEAM PROJECT
−
|[[media:Am27c256.pdf|AMD 32Kx8 EPROM Datasheet]]<br />[[media:Cy7c199n_8.pdf|Cypress 32Kx8 SRAM]]<br />[[media:MT4LC4M16R6.pdf|Micron 4Mx16 EDO DRAM]]<br />[[media:8Gb_DDR4_SDRAM.pdf|Micron 8 Gb DDR4 DRAM]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]<br />RSRC VHDL Supplied by the Instructor
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|Homework 9
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|Homework 8
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|25
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|26
 
|APR 18
 
|APR 18
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|1-Bus vs. 2-Bus vs. 3-Bus RSRC<br />3-Bus RSRC Register File<br />Basic Pipelined SRC/RSRC<br />Intel 8086 Bus Architecture<br />RSRC Instruction Set Review<br />RSRC Architecture Review
+
|TEAM PROJECT
−
|[[media:1_BUS_RSRC_BLOCK_DIAGRAM.pdf|1-Bus SRC Block Diagram (From Heuring and Jordan)]]<br />[[media:2_BUS_RSRC_BLOCK_DIAGRAM.pdf|2-Bus SRC Block Diagram (From Heuring and Jordan)]]<br />[[media:3_BUS_RSRC_BLOCK_DIAGRAM.pdf|3-Bus SRC Block Diagram (From Heuring and Jordan)]]<br />[[media:3_BUS_RSRC_REGFILE.pdf|3-Bus SRC Register File (From Heuring and Jordan)]]<br />[[media:BasicPipelinedSRC.pdf |Basic Pipelined SRC/RSRC]]<br />[[media:Intel_8086_Block_Diagram.pdf|Intel 8086 Block Diagram]]<br />[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]<br />[[media:The_RSRC_SRC_Instruction_Set.pdf|The RSRC Instruction Set]]
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|26
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|27
 
|APR 23
 
|APR 23
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|Difference Engine in C (x86) w/Assembly<br />Review
+
|TEAM PROJECT
−
|[[media:Difference_Engine_in_C.pdf|Difference Engine in C (x86)]]
+
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|Homework 9
 
  
 
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|27
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|28
 
|APR 25
 
|APR 25
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|[[media:Exam -3 Stick Diagram.pdf|Exam 3]]
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|PROJECT PRESENTATIONS
 
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Latest revision as of 20:42, 8 January 2019

CSE 462M SPRING 20xx
LECTURE DATE TOPICS PREPARATION ASSIGNED DUE
1 JAN 15 Course Introduction
VGA Video
Vivado Clocking Wizard
VGA Skeleton VHDL
NEXYS4 DDR Dev Board Manual
NEXYS4 DDR Dev Board Schematic
VHDL Tutorial
Xilinx Vivado Tutorial 		Course Introduction
VGA Video
Vivado Clocking Wizard Tutorial
VGA VHDL Skeleton
Digilent NEXYS 4 DDR Development Board Manual
Digilent NEXYS 4 DDR Development Board Schematics
VHDL Tutorial
Xilinx Vivado Tutorial 		Homework 1
2 JAN 17
3 JAN 22 Bit-Mapped Displays
Vivado Block RAM
COE Files
PCB Fundamentals
CAD Drafting Terminology
The ExpressPCB CAD Tool
ExpressPCB Board Properties
Advanced PCB Concepts 		Vivado Block RAM Tutorial
Example COE File
PCB Technology Article
Drafting Manual
CAD Dimensioning Textbook
ExpresPCB CAD Tool
Express PCB Board Matrix
Reflection Lecture
MS&T Trace Impedance Calculator
Maximum ExpressPCB Trace Impedance 		Homework 2 Homework 1
4 JAN 24
5 JAN 29 Character Displays
PCB Power and Ground Considerations
Project Gantt Chart 		Project Gantt Chart Homework 3 Homework 2
6 JAN 31
7 FEB 5 Semester Project Assignment
Semester Project Paper Format
FPGA Configuration Concepts
FPGA Power Requirements 		Project Assignment
Paper Requirements
Xilinx Spartan 6 FPGA Configuration User Guide
Xilnx Spartan 6 LX Family Switching Characteristics 		Semester Project Homework 3
8 FEB 7 TEAM PROJECT
9 FEB 12 TEAM PROJECT
10 FEB 14 TEAM PROJECT
11 FEB 19 TEAM PROJECT
12 FEB 21 TEAM PROJECT
13 FEB 26 TEAM PROJECT
14 FEB 28 TEAM PROJECT
15 MAR 5 TEAM PROJECT
16 MAR 7 TEAM PROJECT
MAR 12 SPRING BREAK
MAR 14 SPRING BREAK
17 MAR 19 TEAM PROJECT
18 MAR 21 TEAM PROJECT
19 MAR 26 TEAM PROJECT
20 MAR 28 TEAM PROJECT
21 APR 2 TEAM PROJECT
22 APR 4 TEAM PROJECT
23 APR 9 TEAM PROJECT
24 APR 11 TEAM PROJECT


25 APR 16 TEAM PROJECT
26 APR 18 TEAM PROJECT
27 APR 23 TEAM PROJECT
28 APR 25 PROJECT PRESENTATIONS
Retrieved from "http://classes.engineering.wustl.edu/cse462/index.php?title=Syllabus&oldid=1099"