Difference between revisions of "Lecture Notes"
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| − | *[[media: | + | *[[media:CSE_462M_COURSE_INTRODUCTION.pdf|Course Introduction]] |
| − | *[[media: | + | |
| − | *[[media: | + | |
| − | *[[media: | + | *[[media:0714IFD1.pdf|Use Advanced PCB Technology to Produce 50% Smaller Product Designs]] |
| − | *[[media: | + | *[[media:Reflection_Lecture.pdf|Reflection Lecture]] |
| − | *[[media: | + | *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] |
| − | *[[media: | + | *[[media:Lumped_Lecture.pdf|Lumped Lecture]] |
| − | *[[media: | + | *[[media:ExpressPCB-Service-Matrix-12-7-2016.pdf|ExpressPCB Board Specifications]] |
| − | *[[media: | + | *[[media:Maximum_ExpressPCB_Trace_Impedance.pdf|Maximum ExpressPCB Trace Impedance]] |
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| + | *[[media:NTSC_Video.pdf|NTSC Video]] | ||
| + | *[[media:HP_Mini_10_VGA_HS_and_VS.pdf|HP Mini 10 VGA HS and VS Signals]] | ||
| + | |||
| + | |||
*[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Lecture]] | *[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Lecture]] | ||
| − | *[[media: | + | *[[media:FIFO_TUTORIAL.pdf|Xilinx ISE 14.7 FIFO Tutorial]] |
| + | *[[media:Dualport_RAM_Tutorial.pdf|Xilinx ISE 14.7 Dualport RAM Tutorial]] | ||
| + | *[[media:DCM_Tutorial.pdf|Xilinx ISE 14.7 DCM Tutorial]] | ||
| + | *[[media:ISE_VGA_Tutorial.pdf|Xilinx ISE 14.7 VGA Tutorial]] | ||
| + | *[[media:Using_LVDS_Inputs.pdf|Xilinx ISE 14.7 LVDS Input Tutorial]] | ||
| + | *[[media:Simulation_Tutorial.pdf|Xilinx ISE 14.7 Simulation Tutorial]] | ||
| + | *[[media:MCS_File_Tutorial.pdf|Xilinx ISE 14.7 MCS File Tutorial]] | ||
| + | *[[media:Vga.pdf|Xilinx ISE 14.7 Digilent Spartan 3E Board VGA UCF File]] | ||
| + | *[[media:loopback.pdf|Xilnix ISE 14.7 Digilent Spartan 3E Board Loopback UCF File (Instructor Only)]] | ||
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| + | *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Machine Example]] | ||
*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
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| − | + | *[[media:Employment Contract - Clean.pdf|Example Corporate Employment Contract]] | |
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| − | *[[media:Employment Contract - Clean.pdf|Employment Contract]] | ||
Links: | Links: | ||
| − | + | [http://www.fpga4fun.com/HDMI.html HDMI Info] | |
| − | |||
| − | [http://www. | ||
| − | [http://www. | + | [http://www.epanorama.net/documents/pc/vga_timing.html VGA Timing] |
| − | [http:// | + | [http://emclab.mst.edu/pcbtlc2/ PCB Trace Impedance Calculator] |
| − | [http://www. | + | [http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_constraints_timing_strategies.htm Xilinx ISE Timing Constraints Strategies] |
| − | [http://www. | + | [http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pim_c_introduction_indirect_programming.htm Introduction to Xilinx Indirect Programming] |
| − | [http://www. | + | [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] |
| − | [http://www. | + | [http://www.ieee.org/about/corporate/governance/p7-8.html IEEE Code of Ethics] |
Latest revision as of 16:45, 12 January 2018
- Use Advanced PCB Technology to Produce 50% Smaller Product Designs
- Reflection Lecture
- Oscillators and Clock Distribution
- Lumped Lecture
- ExpressPCB Board Specifications
- Maximum ExpressPCB Trace Impedance
- VHDL Lecture
- Xilinx ISE 14.7 FIFO Tutorial
- Xilinx ISE 14.7 Dualport RAM Tutorial
- Xilinx ISE 14.7 DCM Tutorial
- Xilinx ISE 14.7 VGA Tutorial
- Xilinx ISE 14.7 LVDS Input Tutorial
- Xilinx ISE 14.7 Simulation Tutorial
- Xilinx ISE 14.7 MCS File Tutorial
- Xilinx ISE 14.7 Digilent Spartan 3E Board VGA UCF File
- Xilnix ISE 14.7 Digilent Spartan 3E Board Loopback UCF File (Instructor Only)
- State Equal Output Moore Machine Example
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
Links:
PCB Trace Impedance Calculator
Xilinx ISE Timing Constraints Strategies
