Difference between revisions of "General Information"
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Exam #1: February 15, 2017 | Exam #1: February 15, 2017 | ||
| − | Final Exam: May 9, 2017, 1-3 p.m. | + | Final Exam: May 9, 2017, 1-3 p.m., Location: Cupples II 200 |
Project Presentations: April 27, 2017 | Project Presentations: April 27, 2017 | ||
Revision as of 13:34, 11 April 2017
Instructor, William D. Richard, Ph.D., 538 Jolley Hall, 314-935-4676, wdr@wustl.edu
Office Hours: Monday and Wednesday, 9:00-11:00 a.m. or by appointment
Course Web Page: http://classes.engineering.wustl.edu/cse462/index.php/Main_Page
Text: NA (You should have access to a VHDL reference.)
Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Location: Cupples II 200
Exam #1: February 15, 2017
Final Exam: May 9, 2017, 1-3 p.m., Location: Cupples II 200
Project Presentations: April 27, 2017
Paper Due: April 28, 2017 by 5 p.m.
Grading: Two exams, 20% each. Homework: 10%. Project: 50%.
Homework: Homework will be assigned weekly prior to the first exam. Homework turned in at the start of class on the due date will be graded by the instructor. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.
