Difference between revisions of "Syllabus"

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|2
 
|2
 
|JAN 26
 
|JAN 26
|Vivado Block RAM
+
|Vivado Block RAM<br />COE Files
|[[media:Vivado_Block_RAM_Tutorial.pdf|Vivado Block RAM Tutorial]]
+
|[[media:Vivado_Block_RAM_Tutorial.pdf|Vivado Block RAM Tutorial]]<br />[[media:Example_COE_File.pdf|Example COE File]]
 
|Homework 2
 
|Homework 2
 
|Homework 1
 
|Homework 1

Revision as of 17:30, 26 January 2018

SPRING 2018
LECTURE DATE TOPICS PREPARATION ASSIGNED DUE
1 JAN 19 Course Introduction
VGA Video
Vivado Clocking Wizard
VGA Skeleton VHDL
NEXYS4 DDR Dev Board Manual
NEXYS4 DDR Dev Board Schematic
VHDL Tutorial
Xilinx Vivado Tutorial
Course Introduction
VGA Video
Vivado Clocking Wizard Tutorial
VGA VHDL Skeleton
Digilent NEXYS 4 DDR Development Board Manual
Digilent NEXYS 4 DDR Development Board Schematics
VHDL Tutorial
Xilinx Vivado Tutorial
Homework 1
2 JAN 26 Vivado Block RAM
COE Files
Vivado Block RAM Tutorial
Example COE File
Homework 2 Homework 1
3 FEB 2 Homework 3 Homework 2
4 FEB 9 Semester Project Homework 3
5 FEB 16
6 FEB 23
7 MAR 2
8 MAR 9
MAR 16 SPRING BREAK
9 MAR 23
10 MAR 30
11 APR 6
12 APR 13
13 APR 20
14 APR 27
14 MAY 7 PROJECT PRESENTATIONS