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20:31, 26 April 2016
AsynchArt.pdf
(
file
)
140 KB
Wdr
1
14:01, 19 April 2016
CDC Lecture 2016.pdf
(
file
)
1.13 MB
Wdr
1
18:01, 13 April 2016
Bist.pdf
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file
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287 KB
Wdr
1
17:59, 13 April 2016
Fsmtest.pdf
(
file
)
359 KB
Wdr
1
17:56, 13 April 2016
Test.pdf
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file
)
160 KB
Wdr
1
14:33, 12 April 2016
Designing the Edge-Triggered D Flip-Flop.pdf
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file
)
209 KB
Wdr
1
19:31, 7 April 2016
Designing a Sequence Detector.pdf
(
file
)
229 KB
Wdr
1
22:18, 5 April 2016
Kohavi Text Example.pdf
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file
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244 KB
Wdr
1
13:56, 29 March 2016
BCP Reduction Techniques.pdf
(
file
)
75 KB
Wdr
1
15:50, 3 March 2016
Definition of Prime Compatible.pdf
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file
)
93 KB
Wdr
1
15:58, 24 April 2014
The Reflected Binary (Gray) Code.pdf
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file
)
81 KB
Wdr
1
15:51, 22 April 2014
Oscillators and Clock Distribution.pdf
(
file
)
414 KB
Wdr
1
15:23, 22 April 2014
Designing an Asynchronous Counter.pdf
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file
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75 KB
Wdr
1
15:23, 16 April 2014
Cucs-033-94.pdf
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file
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240 KB
Wdr
1
15:00, 16 April 2014
S40C18 DataSheet.pdf
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file
)
926 KB
Wdr
1
19:18, 14 April 2014
Introduction to Asynchronous Circuits.pdf
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file
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330 KB
Wdr
1
18:52, 10 April 2014
Asynchronous.pdf
(
file
)
239 KB
Wdr
1
20:04, 4 April 2014
Designing the SR Latch.pdf
(
file
)
97 KB
Wdr
1
16:02, 2 April 2014
How Fast Can We Clock A Circuit.pdf
(
file
)
76 KB
Wdr
1
14:18, 2 April 2014
Metastability Lecture.pdf
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file
)
50 KB
Wdr
1
18:42, 1 April 2014
Zar Metastability Lecture.pdf
(
file
)
507 KB
Wdr
1
15:55, 24 March 2014
Prime Compatibles Example Revised.pdf
(
file
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187 KB
Wdr
1
20:10, 21 March 2014
Simplification of Incompletely Specified Machines 1.pdf
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file
)
141 KB
Wdr
1
18:07, 21 March 2014
Simplification of Incompletely Specified Machines 2.pdf
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file
)
83 KB
Wdr
1
15:22, 21 March 2014
State Assignment.pdf
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file
)
135 KB
Wdr
1
16:20, 19 March 2014
Cmos-clock-datasheet.pdf
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file
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155 KB
Wdr
1
16:01, 6 March 2014
Simplification of Incompletely Specified Machines.pdf
(
file
)
139 KB
Wdr
1
17:16, 26 February 2014
ISE Simulator Screenshot 2.png
(
file
)
73 KB
Wdr
1
17:14, 26 February 2014
ISE Simulator Screenshot 1.png
(
file
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93 KB
Wdr
1
20:25, 25 February 2014
StateEqualOutputWithTiming2.png
(
file
)
125 KB
Wdr
1
20:05, 25 February 2014
StateEqualOutputSimulationWithTiming.pdf
(
file
)
173 KB
Wdr
1
21:52, 20 February 2014
DefaultV5SynthesisReport.txt
(
file
)
15 KB
Wdr
1
21:49, 20 February 2014
FIGURE7DOT4THREESTATES.png
(
file
)
35 KB
Wdr
1
21:44, 20 February 2014
FIGURE7DOT4V5.png
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file
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143 KB
Wdr
1
21:43, 20 February 2014
FIGURE7DOT4.png
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file
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116 KB
Wdr
1
20:06, 20 February 2014
Minimizing Completely Specified Machines.pdf
(
file
)
59 KB
Wdr
1
19:27, 20 February 2014
Definitions and Theorems for Sequential Machines.pdf
(
file
)
111 KB
Wdr
1
16:50, 20 February 2014
Stateequaloutputsynthesisreport4.txt
(
file
)
16 KB
Wdr
1
16:49, 20 February 2014
StateEqualOutputSimulation4.pdf
(
file
)
58 KB
Wdr
1
16:44, 20 February 2014
Stateequaloutput4.vhd
(
file
)
2 KB
Wdr
1
16:41, 20 February 2014
StateEqualOutputTechnology4.pdf
(
file
)
12 KB
Wdr
1
17:19, 19 February 2014
State Equal Output Moore Example Fixed.pdf
(
file
)
101 KB
Wdr
1
21:37, 18 February 2014
Stateequaloutputsynthesisreport3.txt
(
file
)
16 KB
Wdr
1
21:35, 18 February 2014
StateEqualOutputTechnology3.pdf
(
file
)
13 KB
Wdr
1
21:35, 18 February 2014
StateEqualOutputSimulation3.pdf
(
file
)
62 KB
Wdr
1
21:34, 18 February 2014
Stateequaloutput3.vhd
(
file
)
2 KB
Wdr
1
21:14, 18 February 2014
StateEqualOutputSimulation2.pdf
(
file
)
57 KB
Wdr
1
21:12, 18 February 2014
StateEqualOutputSimulation.pdf
(
file
)
57 KB
Wdr
1
20:25, 18 February 2014
Stateequaloutputsynthesisreport2.txt
(
file
)
16 KB
Wdr
1
20:15, 18 February 2014
Stateequaloutput2.vhd
(
file
)
2 KB
Wdr
1
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