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Altera Logic Efficiency Analysis.pdf ; 1.09 MB
- Altera vs Xilinx.pdf ; 949 KB
Arctanbit0.txt ; 64 KB
- Arctanbit0output.txt ; 8 KB
- AsynchArt.pdf ; 140 KB
- Asynchronous.pdf ; 239 KB
- BCP Reduction Techniques.pdf ; 75 KB
- BDDs.pdf ; 97 KB
- Bist.pdf ; 287 KB
- Bit Zero Optimal LUTs.pdf ; 33 KB
- Boole’s Expansion Theorem.pdf ; 482 KB
- CDC Lecture 2016.pdf ; 1.13 MB
CLOCKGATE.vhd ; 601 bytes
Clocked NOR Latch.jpg 517 × 229; 12 KB
- Clockgate.pdf ; 9 KB
- Cmos-clock-datasheet.pdf ; 155 KB
- Cucs-033-94.pdf ; 240 KB
- CyclicExample.txt ; 249 bytes
- CyclicOutput.txt ; 105 bytes
- Cypress 2KX9 FIFO.pdf ; 644 KB
- D FLIP FLOP.vhd ; 791 bytes
- Decomposition By Expansion.pdf ; 277 KB
- DefaultV1SynthesisReport.txt ; 16 KB
- DefaultV2SynthesisReport.txt ; 16 KB
- DefaultV3SynthesisReport.txt ; 15 KB
- DefaultV4SynthesisReport.txt ; 16 KB
- DefaultV5SynthesisReport.txt ; 15 KB
- Designing a Sequence Detector.pdf ; 229 KB
- Designing the SR Latch.pdf ; 97 KB
- Dflopsim.pdf ; 9 KB
- Dflopsim2.pdf ; 9 KB
- Don't Cares.pdf ; 55 KB
Edge-Triggered D Flip-Flop.jpg 814 × 467; 28 KB
Edwin Robbins.jpg 1,630 × 1,222; 276 KB
- Espresso.zip ; 81 KB
- EspressoExample.txt ; 242 bytes
- EspressoOutput.txt ; 106 bytes
- Example1.vhd ; 443 bytes
- Example10.vhd ; 171 KB
- Example10Technology.pdf ; 25 KB
- Example10TechnologyPH.pdf ; 23 KB
- Example11.vhd ; 174 KB
- Example11Technology.pdf ; 28 KB
- Example11TechnologyPH.pdf ; 24 KB
