Lecture Notes

LOGIC MINIMIZATION

• Standard Cell Example
• Karnaugh Maps
• Synthesis of Two-Level Circuits
• Quine-McCluskey Example
• UCP Reduction Techniques
• Espresso Example
• Espresso Example Output
• Espresso Cyclic Example
• Espresso Cyclic Example Output
• Don't Cares
• Multiple Output Functions
• VHDL Example 1
• VHDL Example 1 Synthesized RTL Schematic Default Settings
• VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings
• VHDL Example 2 (Quine-McCluskey Example)
• VHDL Example 2 Synthesized RTL Schematic Default Settings
• VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings
• VHDL Example 3 (12-bit Arctan Function)
• VHDL Example 4 (12-bit Arctan Function MSB)
• VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)
• VHDL Example 5 (12-bit Arctan Function Bit 10)
• VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)
• VHDL Example 6 (12-bit Arctan Function Bit 9)
• VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)
• VHDL Example 7 (12-bit Arctan Function Bit 8)
• VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)
• VHDL Example 8 (12-bit Arctan Function Bit 0)
• VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)
• VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)
• VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)
• VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)
• VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)
• VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)
• VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)
• VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)
• VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)
• VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)
• Bit Zero Optimal LUTS
• Decomposition By Expansion
• Altera vs. Xilinx
• Xilinx vs. Altera
• Altera Logic Efficiency Analysis
• Altera FPGA Architecture White Paper

SEQUENTIAL SYSTEMS

• Figure 7.4 VHDL Description Version 1
• Xilinx Spartan 6 Technology Map Schematic Default Settings
• Default Version 1 Synthesis Report
• Version 1 ModelSim Simulation
• Figure 7.4 VHDL Description Version 2
• Default Version 2 Synthesis Report
• Figure 7.4 VHDL Description Version 3
• Default Version 3 Synthesis Report
• VHDL Description Version 4 (3 states)
• Version 4 ModelSim Simulation
• Default Version 4 Synthesis Report
• XST User Guide (See Page 276 for Compact State Encoding)
• Redundant FSM With Five States From Class
• Simplification of Completely Specified Machines by Implication Tables
• Definitions and Theorems for Sequential Machines
• Simplification of Incompletely Specified Machines
• Prime Compatibles Example from Hachtel and Somenzi

FINITE AUTOMATA

http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf

ASYNCHRONOUS CIRCUITS AND METASTABILITY

• NOR Latch
• NOR Latch VHDL Description
• NOR Latch VHDL Simulation
• Clocked NOR Latch
• Edge-Triggered D Flip-Flop
• Edge-Triggered D Flip-Flop VHDL Description
• Edge-Triggered D Flip-Flop VHDL Simulation
• Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation
• Anomalous Behavior of Synchronizer and Arbiter Circuits
• Measured Flip-Flop Responses to Marginal Triggering
• David M. Zar Metastability Lecture
• David M. Zar Fundamental Mode Design Example VHDL
• David M. Zar Fundamental Mode Design Example Simulation
• State Assignment
• Cypress 2Kx9 Sync FIFO